Module xmc4800::gpdma1::maskblock

Mask for Raw IntBlock Status

Structs

• MASKBLOCK_SPEC
  Mask for Raw IntBlock Status

Enums

• CH0_A
  Mask bit for channel 0
• CH1_A
  Mask bit for channel 1
• CH2_A
  Mask bit for channel 2
• CH3_A
  Mask bit for channel 3
• WE_CH0_A
  Write enable for mask bit of channel 0
• WE_CH1_A
  Write enable for mask bit of channel 1
• WE_CH2_A
  Write enable for mask bit of channel 2
• WE_CH3_A
  Write enable for mask bit of channel 3

Type Aliases

• CH0_R
  Field CH0 reader - Mask bit for channel 0
• CH0_W
  Field CH0 writer - Mask bit for channel 0
• CH1_R
  Field CH1 reader - Mask bit for channel 1
• CH1_W
  Field CH1 writer - Mask bit for channel 1
• CH2_R
  Field CH2 reader - Mask bit for channel 2
• CH2_W
  Field CH2 writer - Mask bit for channel 2
• CH3_R
  Field CH3 reader - Mask bit for channel 3
• CH3_W
  Field CH3 writer - Mask bit for channel 3
• R
  Register MASKBLOCK reader
• W
  Register MASKBLOCK writer
• WE_CH0_W
  Field WE_CH0 writer - Write enable for mask bit of channel 0
• WE_CH1_W
  Field WE_CH1 writer - Write enable for mask bit of channel 1
• WE_CH2_W
  Field WE_CH2 writer - Write enable for mask bit of channel 2
• WE_CH3_W
  Field WE_CH3 writer - Write enable for mask bit of channel 3