Module xmc4400::gpdma0::masktfr [−][src]
Expand description
Mask for Raw IntTfr Status
Structs
Field CH0 reader - Mask bit for channel 0
Field CH0 writer - Mask bit for channel 0
Field CH1 reader - Mask bit for channel 1
Field CH1 writer - Mask bit for channel 1
Field CH2 reader - Mask bit for channel 2
Field CH2 writer - Mask bit for channel 2
Field CH3 reader - Mask bit for channel 3
Field CH3 writer - Mask bit for channel 3
Field CH4 reader - Mask bit for channel 4
Field CH4 writer - Mask bit for channel 4
Field CH5 reader - Mask bit for channel 5
Field CH5 writer - Mask bit for channel 5
Field CH6 reader - Mask bit for channel 6
Field CH6 writer - Mask bit for channel 6
Field CH7 reader - Mask bit for channel 7
Field CH7 writer - Mask bit for channel 7
Mask for Raw IntTfr Status
Register MASKTFR reader
Register MASKTFR writer
Field WE_CH0 writer - Write enable for mask bit of channel 0
Field WE_CH1 writer - Write enable for mask bit of channel 1
Field WE_CH2 writer - Write enable for mask bit of channel 2
Field WE_CH3 writer - Write enable for mask bit of channel 3
Field WE_CH4 writer - Write enable for mask bit of channel 4
Field WE_CH5 writer - Write enable for mask bit of channel 5
Field WE_CH6 writer - Write enable for mask bit of channel 6
Field WE_CH7 writer - Write enable for mask bit of channel 7
Enums
Mask bit for channel 0
Mask bit for channel 1
Mask bit for channel 2
Mask bit for channel 3
Mask bit for channel 4
Mask bit for channel 5
Mask bit for channel 6
Mask bit for channel 7
Write enable for mask bit of channel 0
Write enable for mask bit of channel 1
Write enable for mask bit of channel 2
Write enable for mask bit of channel 3
Write enable for mask bit of channel 4
Write enable for mask bit of channel 5
Write enable for mask bit of channel 6
Write enable for mask bit of channel 7