1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529
#[doc = "Reader of register ASCTRL"] pub type R = crate::R<u32, super::ASCTRL>; #[doc = "Writer for register ASCTRL"] pub type W = crate::W<u32, super::ASCTRL>; #[doc = "Register ASCTRL `reset()`'s with value 0"] impl crate::ResetValue for super::ASCTRL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Source-specific Result Register\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum SRCRESREG_A { #[doc = "0: Use GxCHCTRy.RESREG to select a group result register"] VALUE1 = 0, #[doc = "1: Store result in group result register GxRES1"] VALUE2 = 1, #[doc = "15: Store result in group result register GxRES15"] VALUE3 = 15, } impl From<SRCRESREG_A> for u8 { #[inline(always)] fn from(variant: SRCRESREG_A) -> Self { variant as _ } } #[doc = "Reader of field `SRCRESREG`"] pub type SRCRESREG_R = crate::R<u8, SRCRESREG_A>; impl SRCRESREG_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, SRCRESREG_A> { use crate::Variant::*; match self.bits { 0 => Val(SRCRESREG_A::VALUE1), 1 => Val(SRCRESREG_A::VALUE2), 15 => Val(SRCRESREG_A::VALUE3), i => Res(i), } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == SRCRESREG_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == SRCRESREG_A::VALUE2 } #[doc = "Checks if the value of the field is `VALUE3`"] #[inline(always)] pub fn is_value3(&self) -> bool { *self == SRCRESREG_A::VALUE3 } } #[doc = "Write proxy for field `SRCRESREG`"] pub struct SRCRESREG_W<'a> { w: &'a mut W, } impl<'a> SRCRESREG_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SRCRESREG_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Use GxCHCTRy.RESREG to select a group result register"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(SRCRESREG_A::VALUE1) } #[doc = "Store result in group result register GxRES1"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(SRCRESREG_A::VALUE2) } #[doc = "Store result in group result register GxRES15"] #[inline(always)] pub fn value3(self) -> &'a mut W { self.variant(SRCRESREG_A::VALUE3) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); self.w } } #[doc = "Reader of field `XTSEL`"] pub type XTSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `XTSEL`"] pub struct XTSEL_W<'a> { w: &'a mut W, } impl<'a> XTSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); self.w } } #[doc = "Reader of field `XTLVL`"] pub type XTLVL_R = crate::R<bool, bool>; #[doc = "Trigger Operating Mode\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum XTMODE_A { #[doc = "0: No external trigger"] VALUE1 = 0, #[doc = "1: Trigger event upon a falling edge"] VALUE2 = 1, #[doc = "2: Trigger event upon a rising edge"] VALUE3 = 2, #[doc = "3: Trigger event upon any edge"] VALUE4 = 3, } impl From<XTMODE_A> for u8 { #[inline(always)] fn from(variant: XTMODE_A) -> Self { variant as _ } } #[doc = "Reader of field `XTMODE`"] pub type XTMODE_R = crate::R<u8, XTMODE_A>; impl XTMODE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> XTMODE_A { match self.bits { 0 => XTMODE_A::VALUE1, 1 => XTMODE_A::VALUE2, 2 => XTMODE_A::VALUE3, 3 => XTMODE_A::VALUE4, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == XTMODE_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == XTMODE_A::VALUE2 } #[doc = "Checks if the value of the field is `VALUE3`"] #[inline(always)] pub fn is_value3(&self) -> bool { *self == XTMODE_A::VALUE3 } #[doc = "Checks if the value of the field is `VALUE4`"] #[inline(always)] pub fn is_value4(&self) -> bool { *self == XTMODE_A::VALUE4 } } #[doc = "Write proxy for field `XTMODE`"] pub struct XTMODE_W<'a> { w: &'a mut W, } impl<'a> XTMODE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: XTMODE_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "No external trigger"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(XTMODE_A::VALUE1) } #[doc = "Trigger event upon a falling edge"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(XTMODE_A::VALUE2) } #[doc = "Trigger event upon a rising edge"] #[inline(always)] pub fn value3(self) -> &'a mut W { self.variant(XTMODE_A::VALUE3) } #[doc = "Trigger event upon any edge"] #[inline(always)] pub fn value4(self) -> &'a mut W { self.variant(XTMODE_A::VALUE4) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13); self.w } } #[doc = "Write Control for Trigger Configuration\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum XTWC_AW { #[doc = "0: No write access to trigger configuration"] VALUE1 = 0, #[doc = "1: Bitfields XTMODE and XTSEL can be written"] VALUE2 = 1, } impl From<XTWC_AW> for bool { #[inline(always)] fn from(variant: XTWC_AW) -> Self { variant as u8 != 0 } } #[doc = "Write proxy for field `XTWC`"] pub struct XTWC_W<'a> { w: &'a mut W, } impl<'a> XTWC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: XTWC_AW) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "No write access to trigger configuration"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(XTWC_AW::VALUE1) } #[doc = "Bitfields XTMODE and XTSEL can be written"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(XTWC_AW::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `GTSEL`"] pub type GTSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `GTSEL`"] pub struct GTSEL_W<'a> { w: &'a mut W, } impl<'a> GTSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); self.w } } #[doc = "Reader of field `GTLVL`"] pub type GTLVL_R = crate::R<bool, bool>; #[doc = "Write Control for Gate Configuration\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GTWC_AW { #[doc = "0: No write access to gate configuration"] VALUE1 = 0, #[doc = "1: Bitfield GTSEL can be written"] VALUE2 = 1, } impl From<GTWC_AW> for bool { #[inline(always)] fn from(variant: GTWC_AW) -> Self { variant as u8 != 0 } } #[doc = "Write proxy for field `GTWC`"] pub struct GTWC_W<'a> { w: &'a mut W, } impl<'a> GTWC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: GTWC_AW) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "No write access to gate configuration"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(GTWC_AW::VALUE1) } #[doc = "Bitfield GTSEL can be written"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(GTWC_AW::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); self.w } } #[doc = "Timer Mode Enable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMEN_A { #[doc = "0: No timer mode: standard gating mechanism can be used"] VALUE1 = 0, #[doc = "1: Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled"] VALUE2 = 1, } impl From<TMEN_A> for bool { #[inline(always)] fn from(variant: TMEN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `TMEN`"] pub type TMEN_R = crate::R<bool, TMEN_A>; impl TMEN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> TMEN_A { match self.bits { false => TMEN_A::VALUE1, true => TMEN_A::VALUE2, } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == TMEN_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == TMEN_A::VALUE2 } } #[doc = "Write proxy for field `TMEN`"] pub struct TMEN_W<'a> { w: &'a mut W, } impl<'a> TMEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: TMEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "No timer mode: standard gating mechanism can be used"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(TMEN_A::VALUE1) } #[doc = "Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(TMEN_A::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Write Control for Timer Mode\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TMWC_AW { #[doc = "0: No write access to timer mode"] VALUE1 = 0, #[doc = "1: Bitfield TMEN can be written"] VALUE2 = 1, } impl From<TMWC_AW> for bool { #[inline(always)] fn from(variant: TMWC_AW) -> Self { variant as u8 != 0 } } #[doc = "Write proxy for field `TMWC`"] pub struct TMWC_W<'a> { w: &'a mut W, } impl<'a> TMWC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: TMWC_AW) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "No write access to timer mode"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(TMWC_AW::VALUE1) } #[doc = "Bitfield TMEN can be written"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(TMWC_AW::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bits 0:3 - Source-specific Result Register"] #[inline(always)] pub fn srcresreg(&self) -> SRCRESREG_R { SRCRESREG_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 8:11 - External Trigger Input Selection"] #[inline(always)] pub fn xtsel(&self) -> XTSEL_R { XTSEL_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - External Trigger Level"] #[inline(always)] pub fn xtlvl(&self) -> XTLVL_R { XTLVL_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bits 13:14 - Trigger Operating Mode"] #[inline(always)] pub fn xtmode(&self) -> XTMODE_R { XTMODE_R::new(((self.bits >> 13) & 0x03) as u8) } #[doc = "Bits 16:19 - Gate Input Selection"] #[inline(always)] pub fn gtsel(&self) -> GTSEL_R { GTSEL_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bit 20 - Gate Input Level"] #[inline(always)] pub fn gtlvl(&self) -> GTLVL_R { GTLVL_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bit 28 - Timer Mode Enable"] #[inline(always)] pub fn tmen(&self) -> TMEN_R { TMEN_R::new(((self.bits >> 28) & 0x01) != 0) } } impl W { #[doc = "Bits 0:3 - Source-specific Result Register"] #[inline(always)] pub fn srcresreg(&mut self) -> SRCRESREG_W { SRCRESREG_W { w: self } } #[doc = "Bits 8:11 - External Trigger Input Selection"] #[inline(always)] pub fn xtsel(&mut self) -> XTSEL_W { XTSEL_W { w: self } } #[doc = "Bits 13:14 - Trigger Operating Mode"] #[inline(always)] pub fn xtmode(&mut self) -> XTMODE_W { XTMODE_W { w: self } } #[doc = "Bit 15 - Write Control for Trigger Configuration"] #[inline(always)] pub fn xtwc(&mut self) -> XTWC_W { XTWC_W { w: self } } #[doc = "Bits 16:19 - Gate Input Selection"] #[inline(always)] pub fn gtsel(&mut self) -> GTSEL_W { GTSEL_W { w: self } } #[doc = "Bit 23 - Write Control for Gate Configuration"] #[inline(always)] pub fn gtwc(&mut self) -> GTWC_W { GTWC_W { w: self } } #[doc = "Bit 28 - Timer Mode Enable"] #[inline(always)] pub fn tmen(&mut self) -> TMEN_W { TMEN_W { w: self } } #[doc = "Bit 31 - Write Control for Timer Mode"] #[inline(always)] pub fn tmwc(&mut self) -> TMWC_W { TMWC_W { w: self } } }