1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632
#[doc = "Reader of register GUSBCFG"] pub type R = crate::R<u32, super::GUSBCFG>; #[doc = "Writer for register GUSBCFG"] pub type W = crate::W<u32, super::GUSBCFG>; #[doc = "Register GUSBCFG `reset()`'s with value 0x1440"] impl crate::ResetValue for super::GUSBCFG { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x1440 } } #[doc = "Reader of field `TOutCal`"] pub type TOUTCAL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `TOutCal`"] pub struct TOUTCAL_W<'a> { w: &'a mut W, } impl<'a> TOUTCAL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } #[doc = "USB 1.1 Full-Speed Serial Transceiver Select\n\nValue on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum PHYSEL_A { #[doc = "1: USB 1.1 full-speed serial transceiver"] VALUE2 = 1, } impl From<PHYSEL_A> for bool { #[inline(always)] fn from(variant: PHYSEL_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `PHYSel`"] pub type PHYSEL_R = crate::R<bool, PHYSEL_A>; impl PHYSEL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<bool, PHYSEL_A> { use crate::Variant::*; match self.bits { true => Val(PHYSEL_A::VALUE2), i => Res(i), } } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == PHYSEL_A::VALUE2 } } #[doc = "SRP-Capable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum SRPCAP_A { #[doc = "0: SRP capability is not enabled."] VALUE1 = 0, #[doc = "1: SRP capability is enabled."] VALUE2 = 1, } impl From<SRPCAP_A> for bool { #[inline(always)] fn from(variant: SRPCAP_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `SRPCap`"] pub type SRPCAP_R = crate::R<bool, SRPCAP_A>; impl SRPCAP_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> SRPCAP_A { match self.bits { false => SRPCAP_A::VALUE1, true => SRPCAP_A::VALUE2, } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == SRPCAP_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == SRPCAP_A::VALUE2 } } #[doc = "Write proxy for field `SRPCap`"] pub struct SRPCAP_W<'a> { w: &'a mut W, } impl<'a> SRPCAP_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SRPCAP_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "SRP capability is not enabled."] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(SRPCAP_A::VALUE1) } #[doc = "SRP capability is enabled."] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(SRPCAP_A::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "HNP-Capable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum HNPCAP_A { #[doc = "0: HNP capability is not enabled."] VALUE1 = 0, #[doc = "1: HNP capability is enabled."] VALUE2 = 1, } impl From<HNPCAP_A> for bool { #[inline(always)] fn from(variant: HNPCAP_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `HNPCap`"] pub type HNPCAP_R = crate::R<bool, HNPCAP_A>; impl HNPCAP_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> HNPCAP_A { match self.bits { false => HNPCAP_A::VALUE1, true => HNPCAP_A::VALUE2, } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == HNPCAP_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == HNPCAP_A::VALUE2 } } #[doc = "Write proxy for field `HNPCap`"] pub struct HNPCAP_W<'a> { w: &'a mut W, } impl<'a> HNPCAP_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: HNPCAP_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "HNP capability is not enabled."] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(HNPCAP_A::VALUE1) } #[doc = "HNP capability is enabled."] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(HNPCAP_A::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } #[doc = "Reader of field `USBTrdTim`"] pub type USBTRDTIM_R = crate::R<u8, u8>; #[doc = "Write proxy for field `USBTrdTim`"] pub struct USBTRDTIM_W<'a> { w: &'a mut W, } impl<'a> USBTRDTIM_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 10)) | (((value as u32) & 0x0f) << 10); self.w } } #[doc = "UTMIFS Interface Select\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OTGI2CSEL_A { #[doc = "0: UTMI USB 1.1 Full-Speed interface for OTG signals"] VALUE1 = 0, } impl From<OTGI2CSEL_A> for bool { #[inline(always)] fn from(variant: OTGI2CSEL_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `OtgI2CSel`"] pub type OTGI2CSEL_R = crate::R<bool, OTGI2CSEL_A>; impl OTGI2CSEL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<bool, OTGI2CSEL_A> { use crate::Variant::*; match self.bits { false => Val(OTGI2CSEL_A::VALUE1), i => Res(i), } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == OTGI2CSEL_A::VALUE1 } } #[doc = "Write proxy for field `OtgI2CSel`"] pub struct OTGI2CSEL_W<'a> { w: &'a mut W, } impl<'a> OTGI2CSEL_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OTGI2CSEL_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "UTMI USB 1.1 Full-Speed interface for OTG signals"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(OTGI2CSEL_A::VALUE1) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Tx End Delay\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TXENDDELAY_A { #[doc = "0: Normal mode"] VALUE1 = 0, #[doc = "1: Introduce Tx end delay timers"] VALUE2 = 1, } impl From<TXENDDELAY_A> for bool { #[inline(always)] fn from(variant: TXENDDELAY_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `TxEndDelay`"] pub type TXENDDELAY_R = crate::R<bool, TXENDDELAY_A>; impl TXENDDELAY_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> TXENDDELAY_A { match self.bits { false => TXENDDELAY_A::VALUE1, true => TXENDDELAY_A::VALUE2, } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == TXENDDELAY_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == TXENDDELAY_A::VALUE2 } } #[doc = "Write proxy for field `TxEndDelay`"] pub struct TXENDDELAY_W<'a> { w: &'a mut W, } impl<'a> TXENDDELAY_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: TXENDDELAY_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Normal mode"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(TXENDDELAY_A::VALUE1) } #[doc = "Introduce Tx end delay timers"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(TXENDDELAY_A::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Force Host Mode\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FORCEHSTMODE_A { #[doc = "0: Normal Mode"] VALUE1 = 0, #[doc = "1: Force Host Mode"] VALUE2 = 1, } impl From<FORCEHSTMODE_A> for bool { #[inline(always)] fn from(variant: FORCEHSTMODE_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `ForceHstMode`"] pub type FORCEHSTMODE_R = crate::R<bool, FORCEHSTMODE_A>; impl FORCEHSTMODE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> FORCEHSTMODE_A { match self.bits { false => FORCEHSTMODE_A::VALUE1, true => FORCEHSTMODE_A::VALUE2, } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == FORCEHSTMODE_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == FORCEHSTMODE_A::VALUE2 } } #[doc = "Write proxy for field `ForceHstMode`"] pub struct FORCEHSTMODE_W<'a> { w: &'a mut W, } impl<'a> FORCEHSTMODE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: FORCEHSTMODE_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Normal Mode"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(FORCEHSTMODE_A::VALUE1) } #[doc = "Force Host Mode"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(FORCEHSTMODE_A::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); self.w } } #[doc = "Force Device Mode\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FORCEDEVMODE_A { #[doc = "0: Normal Mode"] VALUE1 = 0, #[doc = "1: Force Device Mode"] VALUE2 = 1, } impl From<FORCEDEVMODE_A> for bool { #[inline(always)] fn from(variant: FORCEDEVMODE_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `ForceDevMode`"] pub type FORCEDEVMODE_R = crate::R<bool, FORCEDEVMODE_A>; impl FORCEDEVMODE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> FORCEDEVMODE_A { match self.bits { false => FORCEDEVMODE_A::VALUE1, true => FORCEDEVMODE_A::VALUE2, } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == FORCEDEVMODE_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == FORCEDEVMODE_A::VALUE2 } } #[doc = "Write proxy for field `ForceDevMode`"] pub struct FORCEDEVMODE_W<'a> { w: &'a mut W, } impl<'a> FORCEDEVMODE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: FORCEDEVMODE_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Normal Mode"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(FORCEDEVMODE_A::VALUE1) } #[doc = "Force Device Mode"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(FORCEDEVMODE_A::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `CTP`"] pub type CTP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CTP`"] pub struct CTP_W<'a> { w: &'a mut W, } impl<'a> CTP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bits 0:2 - FS Timeout Calibration"] #[inline(always)] pub fn tout_cal(&self) -> TOUTCAL_R { TOUTCAL_R::new((self.bits & 0x07) as u8) } #[doc = "Bit 6 - USB 1.1 Full-Speed Serial Transceiver Select"] #[inline(always)] pub fn physel(&self) -> PHYSEL_R { PHYSEL_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 8 - SRP-Capable"] #[inline(always)] pub fn srpcap(&self) -> SRPCAP_R { SRPCAP_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 9 - HNP-Capable"] #[inline(always)] pub fn hnpcap(&self) -> HNPCAP_R { HNPCAP_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bits 10:13 - USB Turnaround Time"] #[inline(always)] pub fn usbtrd_tim(&self) -> USBTRDTIM_R { USBTRDTIM_R::new(((self.bits >> 10) & 0x0f) as u8) } #[doc = "Bit 16 - UTMIFS Interface Select"] #[inline(always)] pub fn otg_i2csel(&self) -> OTGI2CSEL_R { OTGI2CSEL_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 28 - Tx End Delay"] #[inline(always)] pub fn tx_end_delay(&self) -> TXENDDELAY_R { TXENDDELAY_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bit 29 - Force Host Mode"] #[inline(always)] pub fn force_hst_mode(&self) -> FORCEHSTMODE_R { FORCEHSTMODE_R::new(((self.bits >> 29) & 0x01) != 0) } #[doc = "Bit 30 - Force Device Mode"] #[inline(always)] pub fn force_dev_mode(&self) -> FORCEDEVMODE_R { FORCEDEVMODE_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - Corrupt Tx packet"] #[inline(always)] pub fn ctp(&self) -> CTP_R { CTP_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bits 0:2 - FS Timeout Calibration"] #[inline(always)] pub fn tout_cal(&mut self) -> TOUTCAL_W { TOUTCAL_W { w: self } } #[doc = "Bit 8 - SRP-Capable"] #[inline(always)] pub fn srpcap(&mut self) -> SRPCAP_W { SRPCAP_W { w: self } } #[doc = "Bit 9 - HNP-Capable"] #[inline(always)] pub fn hnpcap(&mut self) -> HNPCAP_W { HNPCAP_W { w: self } } #[doc = "Bits 10:13 - USB Turnaround Time"] #[inline(always)] pub fn usbtrd_tim(&mut self) -> USBTRDTIM_W { USBTRDTIM_W { w: self } } #[doc = "Bit 16 - UTMIFS Interface Select"] #[inline(always)] pub fn otg_i2csel(&mut self) -> OTGI2CSEL_W { OTGI2CSEL_W { w: self } } #[doc = "Bit 28 - Tx End Delay"] #[inline(always)] pub fn tx_end_delay(&mut self) -> TXENDDELAY_W { TXENDDELAY_W { w: self } } #[doc = "Bit 29 - Force Host Mode"] #[inline(always)] pub fn force_hst_mode(&mut self) -> FORCEHSTMODE_W { FORCEHSTMODE_W { w: self } } #[doc = "Bit 30 - Force Device Mode"] #[inline(always)] pub fn force_dev_mode(&mut self) -> FORCEDEVMODE_W { FORCEDEVMODE_W { w: self } } #[doc = "Bit 31 - Corrupt Tx packet"] #[inline(always)] pub fn ctp(&mut self) -> CTP_W { CTP_W { w: self } } }