Module xmc4300::scu_clk::mlinkclkcr

Multi-Link Clock Control

Structs

• MLINKCLKCR_SPEC
  Multi-Link Clock Control

Enums

• CCUDIV_A
  CCU Clock Divider Enable
• CPUDIV_A
  CPU Clock Divider Enable
• PBDIV_A
  PB Clock Divider Enable
• SYSSEL_A
  System Clock Selection Value
• WDTSEL_A
  WDT Clock Selection Value

Type Aliases

• CCUDIV_R
  Field CCUDIV reader - CCU Clock Divider Enable
• CCUDIV_W
  Field CCUDIV writer - CCU Clock Divider Enable
• CPUDIV_R
  Field CPUDIV reader - CPU Clock Divider Enable
• CPUDIV_W
  Field CPUDIV writer - CPU Clock Divider Enable
• PBDIV_R
  Field PBDIV reader - PB Clock Divider Enable
• PBDIV_W
  Field PBDIV writer - PB Clock Divider Enable
• R
  Register MLINKCLKCR reader
• SYSDIV_R
  Field SYSDIV reader - System Clock Division Value
• SYSDIV_W
  Field SYSDIV writer - System Clock Division Value
• SYSSEL_R
  Field SYSSEL reader - System Clock Selection Value
• SYSSEL_W
  Field SYSSEL writer - System Clock Selection Value
• W
  Register MLINKCLKCR writer
• WDTDIV_R
  Field WDTDIV reader - WDT Clock Divider Value
• WDTDIV_W
  Field WDTDIV writer - WDT Clock Divider Value
• WDTSEL_R
  Field WDTSEL reader - WDT Clock Selection Value
• WDTSEL_W
  Field WDTSEL writer - WDT Clock Selection Value