Module xmc4200::scu_clk

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System Control Unit

Modules§

Structs§

Type Aliases§

  • CCUCLKCR (rw) register accessor: CCU Clock Control Register
  • CGATCLR0 (w) register accessor: Peripheral 0 Clock Gating Clear
  • CGATCLR1 (w) register accessor: Peripheral 1 Clock Gating Clear
  • CGATCLR2 (w) register accessor: Peripheral 2 Clock Gating Clear
  • CGATSET0 (w) register accessor: Peripheral 0 Clock Gating Set
  • CGATSET1 (w) register accessor: Peripheral 1 Clock Gating Set
  • CGATSET2 (w) register accessor: Peripheral 2 Clock Gating Set
  • CGATSTAT0 (r) register accessor: Peripheral 0 Clock Gating Status
  • CGATSTAT1 (r) register accessor: Peripheral 1 Clock Gating Status
  • CGATSTAT2 (r) register accessor: Peripheral 2 Clock Gating Status
  • CLKCLR (w) register accessor: CLK Clear Register
  • CLKSET (w) register accessor: CLK Set Register
  • CLKSTAT (r) register accessor: Clock Status Register
  • CPUCLKCR (rw) register accessor: CPU Clock Control Register
  • DSLEEPCR (rw) register accessor: Deep Sleep Control Register
  • EXTCLKCR (rw) register accessor: External Clock Control
  • MLINKCLKCR (rw) register accessor: Multi-Link Clock Control
  • PBCLKCR (rw) register accessor: Peripheral Bus Clock Control Register
  • SLEEPCR (rw) register accessor: Sleep Control Register
  • SYSCLKCR (rw) register accessor: System Clock Control Register
  • USBCLKCR (rw) register accessor: USB Clock Control Register
  • WDTCLKCR (rw) register accessor: WDT Clock Control Register