Expand description
Peripheral access API for XMC1300 microcontrollers (generated using svd2rust v0.13.1)
You can find an overview of the API here.
Modules§
- bccu0
- BCCU Unit 0
- bccu0_
ch0 - BCCU Unit 0
- bccu0_
de0 - BCCU Unit 0
- ccu40
- Capture Compare Unit 4 - Unit 0
- ccu80
- Capture Compare Unit 8 - Unit 0
- ccu40_
cc40 - Capture Compare Unit 4 - Unit 0
- ccu80_
cc80 - Capture Compare Unit 8 - Unit 0
- comparator
- System Control Unit
- eru0
- Event Request Unit 0
- math
- MATH Unit
- nvm
- NVM Unit
- pau
- PAU Unit
- port0
- Port 0
- port1
- Port 1
- port2
- Port 2
- posif0
- Position Interface 0
- ppb
- Cortex-M0 Private Peripheral Block
- prng
- PRNG Unit
- rtc
- Real Time Clock
- scu_
analog - System Control Unit
- scu_clk
- System Control Unit
- scu_
general - System Control Unit
- scu_
interrupt - System Control Unit
- scu_
power - System Control Unit
- scu_
reset - System Control Unit
- shs0
- Sample and Hold ADC Sequencer
- usic0
- Universal Serial Interface Controller 0
- usic0_
ch0 - Universal Serial Interface Controller 0
- vadc
- Analog to Digital Converter
- vadc_g0
- Analog to Digital Converter
- wdt
- Watch Dog Timer
Structs§
- BCCU0
- BCCU Unit 0
- BCCU0_
CH0 - BCCU Unit 0
- BCCU0_
CH1 - BCCU Unit 0
- BCCU0_
CH2 - BCCU Unit 0
- BCCU0_
CH3 - BCCU Unit 0
- BCCU0_
CH4 - BCCU Unit 0
- BCCU0_
CH5 - BCCU Unit 0
- BCCU0_
CH6 - BCCU Unit 0
- BCCU0_
CH7 - BCCU Unit 0
- BCCU0_
CH8 - BCCU Unit 0
- BCCU0_
DE0 - BCCU Unit 0
- BCCU0_
DE1 - BCCU Unit 0
- BCCU0_
DE2 - BCCU Unit 0
- CBP
- Cache and branch predictor maintenance operations
- CCU40
- Capture Compare Unit 4 - Unit 0
- CCU80
- Capture Compare Unit 8 - Unit 0
- CCU40_
CC40 - Capture Compare Unit 4 - Unit 0
- CCU40_
CC41 - Capture Compare Unit 4 - Unit 0
- CCU40_
CC42 - Capture Compare Unit 4 - Unit 0
- CCU40_
CC43 - Capture Compare Unit 4 - Unit 0
- CCU80_
CC80 - Capture Compare Unit 8 - Unit 0
- CCU80_
CC81 - Capture Compare Unit 8 - Unit 0
- CCU80_
CC82 - Capture Compare Unit 8 - Unit 0
- CCU80_
CC83 - Capture Compare Unit 8 - Unit 0
- COMPARATOR
- System Control Unit
- CPUID
- CPUID
- Core
Peripherals - Core peripherals
- DCB
- Debug Control Block
- DWT
- Data Watchpoint and Trace unit
- ERU0
- Event Request Unit 0
- FPB
- Flash Patch and Breakpoint unit
- FPU
- Floating Point Unit
- ITM
- Instrumentation Trace Macrocell
- MATH
- MATH Unit
- MPU
- Memory Protection Unit
- NVIC
- Nested Vector Interrupt Controller
- NVM
- NVM Unit
- PAU
- PAU Unit
- PORT0
- Port 0
- PORT1
- Port 1
- PORT2
- Port 2
- POSIF0
- Position Interface 0
- PPB
- Cortex-M0 Private Peripheral Block
- PRNG
- PRNG Unit
- Peripherals
- All the peripherals
- RTC
- Real Time Clock
- SCB
- System Control Block
- SCU_
ANALOG - System Control Unit
- SCU_CLK
- System Control Unit
- SCU_
GENERAL - System Control Unit
- SCU_
INTERRUPT - System Control Unit
- SCU_
POWER - System Control Unit
- SCU_
RESET - System Control Unit
- SHS0
- Sample and Hold ADC Sequencer
- SYST
- SysTick: System Timer
- TPIU
- Trace Port Interface Unit
- USIC0
- Universal Serial Interface Controller 0
- USIC0_
CH0 - Universal Serial Interface Controller 0
- USIC0_
CH1 - Universal Serial Interface Controller 0
- VADC
- Analog to Digital Converter
- VADC_G0
- Analog to Digital Converter
- VADC_G1
- Analog to Digital Converter
- WDT
- Watch Dog Timer
Enums§
- Interrupt
- Enumeration of all the interrupts
Constants§
- NVIC_
PRIO_ BITS - Number available in the NVIC for configuring priority