Crate xlsynth_g8r

Modules§

aig
aig_serdes
aig_sim
check_equivalence
cut_db: 4-input cut database support.
cut_db_cli_defaults: Consolidated defaults for cut-db rewriting as used by CLI entrypoints.
diverse_samples
dslx_stitch_pipeline: Simple utility to stitch together pipeline stages defined in DSLX.
gate_builder: The GateBuilder is a builder for a GateFn – it builds up the underlying (AIG) data structure as operations are added.
gate_fn_equiv_report
gatify: Gateification (PIR → GateFn) and associated pre-lowering rewrites.
ir2gate_utils: These are helper routines for the process of mapping XLS IR operations to gates.
ir2gates
ir_aig_sharing: Candidate discovery for mapping PIR node output bits to AIG node outputs.
liberty
liberty_proto
mcmc_logic
netlist
process_ir_path
propose_equiv: Functionality for proposing equivalence classes via concrete simulation.
prove_gate_fn_equiv_common
prove_gate_fn_equiv_varisat: Validates equivalence classes proposed by propose_equiv.
result_proto
test_utils
transforms
use_count
verilog_version: Enumeration of HDL versions that the code generators can emit. Using a dedicated type avoids the ambiguity of passing around a bool.