List of all items
Structs
- apic::Icr
- apic::ioapic::IoApic
- apic::x2apic::X2APIC
- apic::xapic::XAPIC
- bits32::eflags::EFlags
- bits32::paging::IOAddr
- bits32::paging::LargePage
- bits32::paging::PAddr
- bits32::paging::PDEntry
- bits32::paging::PDFlags
- bits32::paging::PTEntry
- bits32::paging::PTFlags
- bits32::paging::Page
- bits32::paging::VAddr
- bits32::task::TaskStateSegment
- bits64::paging::HugePage
- bits64::paging::IOAddr
- bits64::paging::LargePage
- bits64::paging::PAddr
- bits64::paging::PDEntry
- bits64::paging::PDFlags
- bits64::paging::PDPTEntry
- bits64::paging::PDPTFlags
- bits64::paging::PML4Entry
- bits64::paging::PML4Flags
- bits64::paging::PML5Entry
- bits64::paging::PML5Flags
- bits64::paging::PTEntry
- bits64::paging::PTFlags
- bits64::paging::Page
- bits64::paging::VAddr
- bits64::rflags::RFlags
- bits64::segmentation::Descriptor64
- bits64::task::TaskStateSegment
- controlregs::Cr0
- controlregs::Cr4
- controlregs::Xcr0
- cpuid::ApmInfo
- cpuid::CacheInfo
- cpuid::CacheInfoIter
- cpuid::CacheParameter
- cpuid::CacheParametersIter
- cpuid::CpuId
- cpuid::CpuIdResult
- cpuid::DatInfo
- cpuid::DatIter
- cpuid::DirectCacheAccessInfo
- cpuid::EpcSection
- cpuid::ExtendedFeatures
- cpuid::ExtendedProcessorFeatureIdentifiers
- cpuid::ExtendedState
- cpuid::ExtendedStateInfo
- cpuid::ExtendedStateIter
- cpuid::ExtendedTopologyIter
- cpuid::ExtendedTopologyLevel
- cpuid::FeatureInfo
- cpuid::HypervisorInfo
- cpuid::L1CacheTlbInfo
- cpuid::L2And3CacheTlbInfo
- cpuid::L2CatInfo
- cpuid::L3CatInfo
- cpuid::L3MonitoringInfo
- cpuid::MemBwAllocationInfo
- cpuid::MemoryEncryptionInfo
- cpuid::MonitorMwaitInfo
- cpuid::PerformanceMonitoringInfo
- cpuid::PerformanceOptimizationInfo
- cpuid::ProcessorBrandString
- cpuid::ProcessorCapacityAndFeatureInfo
- cpuid::ProcessorFrequencyInfo
- cpuid::ProcessorSerial
- cpuid::ProcessorTopologyInfo
- cpuid::ProcessorTraceInfo
- cpuid::RdtAllocationInfo
- cpuid::RdtMonitoringInfo
- cpuid::SgxInfo
- cpuid::SgxSectionIter
- cpuid::SoCVendorAttributesIter
- cpuid::SoCVendorBrand
- cpuid::SoCVendorInfo
- cpuid::SvmFeatures
- cpuid::ThermalPowerInfo
- cpuid::Tlb1gbPageInfo
- cpuid::TscInfo
- cpuid::VendorInfo
- debugregs::Dr6
- debugregs::Dr7
- dtables::DescriptorTablePointer
- irq::InterruptDescription
- irq::PageFaultError
- segmentation::Descriptor
- segmentation::DescriptorBuilder
- segmentation::SegmentSelector
- vmx::vmcs::control::EntryControls
- vmx::vmcs::control::ExitControls
- vmx::vmcs::control::PinbasedControls
- vmx::vmcs::control::PrimaryControls
- vmx::vmcs::control::SecondaryControls
Enums
- Ring
- apic::ApicId
- apic::DeliveryMode
- apic::DeliveryStatus
- apic::DestinationMode
- apic::DestinationShorthand
- apic::Level
- apic::TriggerMode
- cpuid::Associativity
- cpuid::CacheInfoType
- cpuid::CacheType
- cpuid::DatType
- cpuid::ExtendedRegisterStateLocation
- cpuid::ExtendedRegisterType
- cpuid::Hypervisor
- cpuid::SgxSectionInfo
- cpuid::TopologyType
- debugregs::BreakCondition
- debugregs::BreakSize
- debugregs::Breakpoint
- segmentation::CodeSegmentType
- segmentation::DataSegmentType
- segmentation::SystemDescriptorTypes32
- segmentation::SystemDescriptorTypes64
- vmx::VmFail
Traits
- apic::ApicControl
- random::RdRand
- random::RdSeed
- segmentation::BuildDescriptor
- segmentation::GateDescriptorBuilder
- segmentation::LdtDescriptorBuilder
- segmentation::SegmentDescriptorBuilder
- segmentation::TaskGateDescriptorBuilder
Macros
Functions
- bits32::eflags::clac
- bits32::eflags::stac
- bits32::paging::pd_index
- bits32::paging::pt_index
- bits64::paging::pd_index
- bits64::paging::pdpt_index
- bits64::paging::pml4_index
- bits64::paging::pml5_index
- bits64::paging::pt_index
- bits64::registers::rbp
- bits64::registers::rip
- bits64::registers::rsp
- bits64::rflags::read
- bits64::rflags::set
- bits64::segmentation::load_cs
- bits64::segmentation::rdfsbase
- bits64::segmentation::rdgsbase
- bits64::segmentation::swapgs
- bits64::segmentation::wrfsbase
- bits64::segmentation::wrgsbase
- bits64::sgx::encls_create
- bits64::sgx::encls_eadd
- bits64::sgx::encls_eaug
- bits64::sgx::encls_eblock
- bits64::sgx::encls_edbgrd
- bits64::sgx::encls_edbgwr
- bits64::sgx::encls_eextend
- bits64::sgx::encls_einit
- bits64::sgx::encls_eldb
- bits64::sgx::encls_eldu
- bits64::sgx::encls_emodpr
- bits64::sgx::encls_emodt
- bits64::sgx::encls_epa
- bits64::sgx::encls_eremove
- bits64::sgx::encls_etrack
- bits64::sgx::encls_ewb
- bits64::sgx::enclu_eaccept
- bits64::sgx::enclu_eacceptcopy
- bits64::sgx::enclu_eenter
- bits64::sgx::enclu_eexit
- bits64::sgx::enclu_egetkey
- bits64::sgx::enclu_emodepe
- bits64::sgx::enclu_ereport
- bits64::sgx::enclu_eresume
- bits64::syscall::syscall0
- bits64::syscall::syscall1
- bits64::syscall::syscall2
- bits64::syscall::syscall3
- bits64::syscall::syscall4
- bits64::syscall::syscall5
- bits64::syscall::syscall6
- bits64::vmx::vmclear
- bits64::vmx::vmlaunch
- bits64::vmx::vmptrld
- bits64::vmx::vmptrst
- bits64::vmx::vmread
- bits64::vmx::vmresume
- bits64::vmx::vmwrite
- bits64::vmx::vmxoff
- bits64::vmx::vmxon
- controlregs::cr0
- controlregs::cr0_write
- controlregs::cr2
- controlregs::cr2_write
- controlregs::cr3
- controlregs::cr3_write
- controlregs::cr4
- controlregs::cr4_write
- controlregs::xcr0
- controlregs::xcr0_write
- cpuid::native_cpuid::cpuid_count
- debugregs::dr0
- debugregs::dr0_write
- debugregs::dr1
- debugregs::dr1_write
- debugregs::dr2
- debugregs::dr2_write
- debugregs::dr3
- debugregs::dr3_write
- debugregs::dr6
- debugregs::dr6_write
- debugregs::dr7
- debugregs::dr7_write
- dtables::ldtr
- dtables::lgdt
- dtables::lidt
- dtables::load_ldtr
- dtables::sgdt
- dtables::sidt
- fence::lfence
- fence::mfence
- fence::sfence
- halt
- io::inb
- io::inl
- io::inw
- io::outb
- io::outl
- io::outw
- irq::disable
- irq::enable
- msr::rdmsr
- msr::wrmsr
- random::rdrand16
- random::rdrand32
- random::rdrand64
- random::rdrand_slice
- random::rdseed16
- random::rdseed32
- random::rdseed64
- random::rdseed_slice
- rdpid
- segmentation::cs
- segmentation::ds
- segmentation::es
- segmentation::fs
- segmentation::gs
- segmentation::load_ds
- segmentation::load_es
- segmentation::load_fs
- segmentation::load_gs
- segmentation::load_ss
- segmentation::ss
- task::load_tr
- task::tr
- time::rdtsc
- time::rdtscp
- tlb::flush
- tlb::flush_all
Type Definitions
- bits32::paging::PD
- bits32::paging::PT
- bits64::paging::PD
- bits64::paging::PDPT
- bits64::paging::PML4
- bits64::paging::PML5
- bits64::paging::PT
- vmx::Result
Statics
Constants
- apic::xapic::XAPIC_EOI
- apic::xapic::XAPIC_ESR
- apic::xapic::XAPIC_ICR0
- apic::xapic::XAPIC_ICR1
- apic::xapic::XAPIC_ID
- apic::xapic::XAPIC_IRR0
- apic::xapic::XAPIC_IRR1
- apic::xapic::XAPIC_IRR2
- apic::xapic::XAPIC_IRR3
- apic::xapic::XAPIC_IRR4
- apic::xapic::XAPIC_IRR5
- apic::xapic::XAPIC_IRR6
- apic::xapic::XAPIC_IRR7
- apic::xapic::XAPIC_ISR0
- apic::xapic::XAPIC_ISR1
- apic::xapic::XAPIC_ISR2
- apic::xapic::XAPIC_ISR3
- apic::xapic::XAPIC_ISR4
- apic::xapic::XAPIC_ISR5
- apic::xapic::XAPIC_ISR6
- apic::xapic::XAPIC_ISR7
- apic::xapic::XAPIC_LDR
- apic::xapic::XAPIC_LVT_CMCI
- apic::xapic::XAPIC_LVT_ERROR
- apic::xapic::XAPIC_LVT_LINT0
- apic::xapic::XAPIC_LVT_LINT1
- apic::xapic::XAPIC_LVT_PMI
- apic::xapic::XAPIC_LVT_THERMAL
- apic::xapic::XAPIC_LVT_TIMER
- apic::xapic::XAPIC_PPR
- apic::xapic::XAPIC_SVR
- apic::xapic::XAPIC_TIMER_CURRENT_COUNT
- apic::xapic::XAPIC_TIMER_DIV_CONF
- apic::xapic::XAPIC_TIMER_INIT_COUNT
- apic::xapic::XAPIC_TMR0
- apic::xapic::XAPIC_TMR1
- apic::xapic::XAPIC_TMR2
- apic::xapic::XAPIC_TMR3
- apic::xapic::XAPIC_TMR4
- apic::xapic::XAPIC_TMR5
- apic::xapic::XAPIC_TMR6
- apic::xapic::XAPIC_TMR7
- apic::xapic::XAPIC_TPR
- apic::xapic::XAPIC_VERSION
- bits32::paging::BASE_PAGE_SHIFT
- bits32::paging::BASE_PAGE_SIZE
- bits32::paging::CACHE_LINE_SIZE
- bits32::paging::LARGE_PAGE_SIZE
- bits32::paging::PAGE_SIZE_ENTRIES
- bits64::paging::BASE_PAGE_SHIFT
- bits64::paging::BASE_PAGE_SIZE
- bits64::paging::CACHE_LINE_SIZE
- bits64::paging::HUGE_PAGE_SIZE
- bits64::paging::LARGE_PAGE_SIZE
- bits64::paging::MAXPHYADDR
- bits64::paging::MAXVADDR
- bits64::paging::MAXVADDR_BITS
- bits64::paging::PAGE_SIZE_ENTRIES
- bits64::paging::PML4_SLOT_SIZE
- cpuid::CACHE_INFO_TABLE
- debugregs::BREAKPOINT_REGS
- irq::ALIGNMENT_CHECK_VECTOR
- irq::BOUND_RANGE_EXCEEDED_VECTOR
- irq::BREAKPOINT_VECTOR
- irq::COPROCESSOR_SEGMENT_OVERRUN_VECTOR
- irq::DEBUG_VECTOR
- irq::DEVICE_NOT_AVAILABLE_VECTOR
- irq::DIVIDE_ERROR_VECTOR
- irq::DOUBLE_FAULT_VECTOR
- irq::GENERAL_PROTECTION_FAULT_VECTOR
- irq::INVALID_OPCODE_VECTOR
- irq::INVALID_TSS_VECTOR
- irq::MACHINE_CHECK_VECTOR
- irq::NONMASKABLE_INTERRUPT_VECTOR
- irq::OVERFLOW_VECTOR
- irq::PAGE_FAULT_VECTOR
- irq::SEGMENT_NOT_PRESENT_VECTOR
- irq::SIMD_FLOATING_POINT_VECTOR
- irq::STACK_SEGEMENT_FAULT_VECTOR
- irq::VIRTUALIZATION_VECTOR
- irq::X87_FPU_VECTOR
- msr::APIC_BASE
- msr::BIOS_UPDT_TRIG
- msr::DEBUGCTLMSR
- msr::EBL_CR_POWERON
- msr::IA32_APERF
- msr::IA32_APIC_BASE
- msr::IA32_A_PMC0
- msr::IA32_A_PMC1
- msr::IA32_A_PMC2
- msr::IA32_A_PMC3
- msr::IA32_A_PMC4
- msr::IA32_A_PMC5
- msr::IA32_A_PMC6
- msr::IA32_A_PMC7
- msr::IA32_BIOS_SIGN_ID
- msr::IA32_BIOS_UPDT_TRIG
- msr::IA32_CLOCK_MODULATION
- msr::IA32_CPU_DCA_CAP
- msr::IA32_CSTAR
- msr::IA32_DCA_0_CAP
- msr::IA32_DEBUGCTL
- msr::IA32_DS_AREA
- msr::IA32_EFER
- msr::IA32_ENERGY_PERF_BIAS
- msr::IA32_FEATURE_CONTROL
- msr::IA32_FIXED_CTR0
- msr::IA32_FIXED_CTR1
- msr::IA32_FIXED_CTR2
- msr::IA32_FIXED_CTR_CTRL
- msr::IA32_FMASK
- msr::IA32_FS_BASE
- msr::IA32_GS_BASE
- msr::IA32_KERNEL_GSBASE
- msr::IA32_LSTAR
- msr::IA32_MC0_ADDR
- msr::IA32_MC0_ADDR1
- msr::IA32_MC0_CTL
- msr::IA32_MC0_CTL2
- msr::IA32_MC0_MISC
- msr::IA32_MC0_STATUS
- msr::IA32_MC10_ADDR1
- msr::IA32_MC10_CTL
- msr::IA32_MC10_CTL2
- msr::IA32_MC10_MISC
- msr::IA32_MC10_STATUS
- msr::IA32_MC11_ADDR1
- msr::IA32_MC11_CTL
- msr::IA32_MC11_CTL2
- msr::IA32_MC11_MISC
- msr::IA32_MC11_STATUS
- msr::IA32_MC12_ADDR1
- msr::IA32_MC12_CTL
- msr::IA32_MC12_CTL2
- msr::IA32_MC12_MISC
- msr::IA32_MC12_STATUS
- msr::IA32_MC13_ADDR1
- msr::IA32_MC13_CTL
- msr::IA32_MC13_CTL2
- msr::IA32_MC13_MISC
- msr::IA32_MC13_STATUS
- msr::IA32_MC14_ADDR1
- msr::IA32_MC14_CTL
- msr::IA32_MC14_CTL2
- msr::IA32_MC14_MISC
- msr::IA32_MC14_STATUS
- msr::IA32_MC15_ADDR1
- msr::IA32_MC15_CTL
- msr::IA32_MC15_CTL2
- msr::IA32_MC15_MISC
- msr::IA32_MC15_STATUS
- msr::IA32_MC16_ADDR1
- msr::IA32_MC16_CTL
- msr::IA32_MC16_CTL2
- msr::IA32_MC16_MISC
- msr::IA32_MC16_STATUS
- msr::IA32_MC17_ADDR1
- msr::IA32_MC17_CTL
- msr::IA32_MC17_CTL2
- msr::IA32_MC17_MISC
- msr::IA32_MC17_STATUS
- msr::IA32_MC18_ADDR1
- msr::IA32_MC18_CTL
- msr::IA32_MC18_CTL2
- msr::IA32_MC18_MISC
- msr::IA32_MC18_STATUS
- msr::IA32_MC19_ADDR1
- msr::IA32_MC19_CTL
- msr::IA32_MC19_CTL2
- msr::IA32_MC19_MISC
- msr::IA32_MC19_STATUS
- msr::IA32_MC1_ADDR
- msr::IA32_MC1_ADDR2
- msr::IA32_MC1_CTL
- msr::IA32_MC1_CTL2
- msr::IA32_MC1_MISC
- msr::IA32_MC1_STATUS
- msr::IA32_MC20_ADDR1
- msr::IA32_MC20_CTL
- msr::IA32_MC20_CTL2
- msr::IA32_MC20_MISC
- msr::IA32_MC20_STATUS
- msr::IA32_MC21_ADDR1
- msr::IA32_MC21_CTL
- msr::IA32_MC21_CTL2
- msr::IA32_MC21_MISC
- msr::IA32_MC21_STATUS
- msr::IA32_MC2_ADDR
- msr::IA32_MC2_ADDR1
- msr::IA32_MC2_CTL
- msr::IA32_MC2_CTL2
- msr::IA32_MC2_MISC
- msr::IA32_MC2_STATUS
- msr::IA32_MC3_ADDR
- msr::IA32_MC3_ADDR1
- msr::IA32_MC3_CTL
- msr::IA32_MC3_CTL2
- msr::IA32_MC3_MISC
- msr::IA32_MC3_STATUS
- msr::IA32_MC4_ADDR
- msr::IA32_MC4_ADDR1
- msr::IA32_MC4_CTL
- msr::IA32_MC4_CTL2
- msr::IA32_MC4_MISC
- msr::IA32_MC4_STATUS
- msr::IA32_MC5_ADDR1
- msr::IA32_MC5_CTL
- msr::IA32_MC5_CTL2
- msr::IA32_MC5_MISC
- msr::IA32_MC5_STATUS
- msr::IA32_MC6_ADDR1
- msr::IA32_MC6_CTL
- msr::IA32_MC6_CTL2
- msr::IA32_MC6_MISC
- msr::IA32_MC6_STATUS
- msr::IA32_MC7_ADDR1
- msr::IA32_MC7_CTL
- msr::IA32_MC7_CTL2
- msr::IA32_MC7_MISC
- msr::IA32_MC7_STATUS
- msr::IA32_MC8_ADDR1
- msr::IA32_MC8_CTL
- msr::IA32_MC8_CTL2
- msr::IA32_MC8_MISC
- msr::IA32_MC8_STATUS
- msr::IA32_MC9_ADDR1
- msr::IA32_MC9_CTL
- msr::IA32_MC9_CTL2
- msr::IA32_MC9_MISC
- msr::IA32_MC9_STATUS
- msr::IA32_MCG_CAP
- msr::IA32_MCG_CTL
- msr::IA32_MCG_STATUS
- msr::IA32_MISC_ENABLE
- msr::IA32_MONITOR_FILTER_LINE_SIZE
- msr::IA32_MONITOR_FILTER_SIZE
- msr::IA32_MPERF
- msr::IA32_MTRRCAP
- msr::IA32_MTRR_DEF_TYPE
- msr::IA32_MTRR_FIX16K_80000
- msr::IA32_MTRR_FIX16K_A0000
- msr::IA32_MTRR_FIX4K_C0000
- msr::IA32_MTRR_FIX4K_C8000
- msr::IA32_MTRR_FIX4K_D0000
- msr::IA32_MTRR_FIX4K_D8000
- msr::IA32_MTRR_FIX4K_E0000
- msr::IA32_MTRR_FIX4K_E8000
- msr::IA32_MTRR_FIX4K_F0000
- msr::IA32_MTRR_FIX4K_F8000
- msr::IA32_MTRR_FIX64K_00000
- msr::IA32_MTRR_PHYSBASE0
- msr::IA32_MTRR_PHYSBASE1
- msr::IA32_MTRR_PHYSBASE2
- msr::IA32_MTRR_PHYSBASE3
- msr::IA32_MTRR_PHYSBASE4
- msr::IA32_MTRR_PHYSBASE5
- msr::IA32_MTRR_PHYSBASE6
- msr::IA32_MTRR_PHYSBASE7
- msr::IA32_MTRR_PHYSBASE8
- msr::IA32_MTRR_PHYSBASE9
- msr::IA32_MTRR_PHYSMASK0
- msr::IA32_MTRR_PHYSMASK1
- msr::IA32_MTRR_PHYSMASK2
- msr::IA32_MTRR_PHYSMASK3
- msr::IA32_MTRR_PHYSMASK4
- msr::IA32_MTRR_PHYSMASK5
- msr::IA32_MTRR_PHYSMASK6
- msr::IA32_MTRR_PHYSMASK7
- msr::IA32_MTRR_PHYSMASK8
- msr::IA32_MTRR_PHYSMASK9
- msr::IA32_P5_MC_ADDR
- msr::IA32_P5_MC_TYPE
- msr::IA32_PACKAGE_THERM_INTERRUPT
- msr::IA32_PACKAGE_THERM_STATUS
- msr::IA32_PAT
- msr::IA32_PEBS_ENABLE
- msr::IA32_PERFEVTSEL0
- msr::IA32_PERFEVTSEL1
- msr::IA32_PERFEVTSEL2
- msr::IA32_PERFEVTSEL3
- msr::IA32_PERFEVTSEL4
- msr::IA32_PERFEVTSEL5
- msr::IA32_PERFEVTSEL6
- msr::IA32_PERFEVTSEL7
- msr::IA32_PERF_CAPABILITIES
- msr::IA32_PERF_CTL
- msr::IA32_PERF_GLOBAL_CTRL
- msr::IA32_PERF_GLOBAL_OVF_CTRL
- msr::IA32_PERF_GLOBAL_STAUS
- msr::IA32_PERF_STATUS
- msr::IA32_PLATFORM_DCA_CAP
- msr::IA32_PLATFORM_ID
- msr::IA32_PMC0
- msr::IA32_PMC1
- msr::IA32_PMC2
- msr::IA32_PMC3
- msr::IA32_PMC4
- msr::IA32_PMC5
- msr::IA32_PMC6
- msr::IA32_PMC7
- msr::IA32_PQR_ASSOC
- msr::IA32_QM_CTR
- msr::IA32_QM_EVTSEL
- msr::IA32_SMBASE
- msr::IA32_SMM_MONITOR_CTL
- msr::IA32_SMRR_PHYSBASE
- msr::IA32_SMRR_PHYSMASK
- msr::IA32_STAR
- msr::IA32_SYSENTER_CS
- msr::IA32_SYSENTER_EIP
- msr::IA32_SYSENTER_ESP
- msr::IA32_THERM_INTERRUPT
- msr::IA32_THERM_STATUS
- msr::IA32_TIME_STAMP_COUNTER
- msr::IA32_TSC_ADJUST
- msr::IA32_TSC_AUX
- msr::IA32_TSC_DEADLINE
- msr::IA32_VMX_BASIC
- msr::IA32_VMX_CR0_FIXED0
- msr::IA32_VMX_CR0_FIXED1
- msr::IA32_VMX_CR4_FIXED0
- msr::IA32_VMX_CR4_FIXED1
- msr::IA32_VMX_CRO_FIXED0
- msr::IA32_VMX_CRO_FIXED1
- msr::IA32_VMX_ENTRY_CTLS
- msr::IA32_VMX_EPT_VPID_CAP
- msr::IA32_VMX_EPT_VPID_ENUM
- msr::IA32_VMX_EXIT_CTLS
- msr::IA32_VMX_FMFUNC
- msr::IA32_VMX_MISC
- msr::IA32_VMX_PINBASED_CTLS
- msr::IA32_VMX_PROCBASED_CTLS
- msr::IA32_VMX_PROCBASED_CTLS2
- msr::IA32_VMX_TRUE_ENTRY_CTLS
- msr::IA32_VMX_TRUE_EXIT_CTLS
- msr::IA32_VMX_TRUE_PINBASED_CTLS
- msr::IA32_VMX_TRUE_PROCBASED_CTLS
- msr::IA32_VMX_VMCS_ENUM
- msr::IA32_VMX_VMFUNC
- msr::IA32_X2APIC_APICID
- msr::IA32_X2APIC_CUR_COUNT
- msr::IA32_X2APIC_DIV_CONF
- msr::IA32_X2APIC_EOI
- msr::IA32_X2APIC_ESR
- msr::IA32_X2APIC_ICR
- msr::IA32_X2APIC_INIT_COUNT
- msr::IA32_X2APIC_IRR0
- msr::IA32_X2APIC_IRR1
- msr::IA32_X2APIC_IRR2
- msr::IA32_X2APIC_IRR3
- msr::IA32_X2APIC_IRR4
- msr::IA32_X2APIC_IRR5
- msr::IA32_X2APIC_IRR6
- msr::IA32_X2APIC_IRR7
- msr::IA32_X2APIC_ISR0
- msr::IA32_X2APIC_ISR1
- msr::IA32_X2APIC_ISR2
- msr::IA32_X2APIC_ISR3
- msr::IA32_X2APIC_ISR4
- msr::IA32_X2APIC_ISR5
- msr::IA32_X2APIC_ISR6
- msr::IA32_X2APIC_ISR7
- msr::IA32_X2APIC_LDR
- msr::IA32_X2APIC_LVT_CMCI
- msr::IA32_X2APIC_LVT_ERROR
- msr::IA32_X2APIC_LVT_LINT0
- msr::IA32_X2APIC_LVT_LINT1
- msr::IA32_X2APIC_LVT_PMI
- msr::IA32_X2APIC_LVT_THERMAL
- msr::IA32_X2APIC_LVT_TIMER
- msr::IA32_X2APIC_PPR
- msr::IA32_X2APIC_SELF_IPI
- msr::IA32_X2APIC_SIVR
- msr::IA32_X2APIC_TMR0
- msr::IA32_X2APIC_TMR1
- msr::IA32_X2APIC_TMR2
- msr::IA32_X2APIC_TMR3
- msr::IA32_X2APIC_TMR4
- msr::IA32_X2APIC_TMR5
- msr::IA32_X2APIC_TMR6
- msr::IA32_X2APIC_TMR7
- msr::IA32_X2APIC_TPR
- msr::IA32_X2APIC_VERSION
- msr::LASTBRANCHFROMIP
- msr::LASTBRANCHTOIP
- msr::LASTINTFROMIP
- msr::LASTINTTOIP
- msr::MC0_ADDR
- msr::MC0_CTL
- msr::MC0_MISC
- msr::MC0_STATUS
- msr::MC1_ADDR
- msr::MC1_CTL
- msr::MC1_MISC
- msr::MC1_STATUS
- msr::MC2_ADDR
- msr::MC2_CTL
- msr::MC2_MISC
- msr::MC2_STATUS
- msr::MC3_ADDR
- msr::MC3_CTL
- msr::MC3_MISC
- msr::MC3_STATUS
- msr::MC4_ADDR
- msr::MC4_CTL
- msr::MC4_MISC
- msr::MC4_STATUS
- msr::MCG_CAP
- msr::MCG_CTL
- msr::MCG_STATUS
- msr::MSR_ALF_ESCR0
- msr::MSR_ALF_ESCR1
- msr::MSR_B0_PMON_BOX_CTRL
- msr::MSR_B0_PMON_BOX_OVF_CTRL
- msr::MSR_B0_PMON_BOX_STATUS
- msr::MSR_B0_PMON_CTR0
- msr::MSR_B0_PMON_CTR1
- msr::MSR_B0_PMON_CTR2
- msr::MSR_B0_PMON_CTR3
- msr::MSR_B0_PMON_EVNT_SEL0
- msr::MSR_B0_PMON_EVNT_SEL1
- msr::MSR_B0_PMON_EVNT_SEL2
- msr::MSR_B0_PMON_EVNT_SEL3
- msr::MSR_B0_PMON_MASK
- msr::MSR_B0_PMON_MATCH
- msr::MSR_B1_PMON_BOX_CTRL
- msr::MSR_B1_PMON_BOX_OVF_CTRL
- msr::MSR_B1_PMON_BOX_STATUS
- msr::MSR_B1_PMON_CTR0
- msr::MSR_B1_PMON_CTR1
- msr::MSR_B1_PMON_CTR2
- msr::MSR_B1_PMON_CTR3
- msr::MSR_B1_PMON_EVNT_SEL0
- msr::MSR_B1_PMON_EVNT_SEL1
- msr::MSR_B1_PMON_EVNT_SEL2
- msr::MSR_B1_PMON_EVNT_SEL3
- msr::MSR_B1_PMON_MASK
- msr::MSR_B1_PMON_MATCH
- msr::MSR_BBL_CR_CTL
- msr::MSR_BBL_CR_CTL3
- msr::MSR_BPU_CCCR0
- msr::MSR_BPU_CCCR1
- msr::MSR_BPU_CCCR2
- msr::MSR_BPU_CCCR3
- msr::MSR_BPU_COUNTER0
- msr::MSR_BPU_COUNTER1
- msr::MSR_BPU_COUNTER2
- msr::MSR_BPU_COUNTER3
- msr::MSR_BPU_ESCR0
- msr::MSR_BPU_ESCR1
- msr::MSR_BSU_ESCR0
- msr::MSR_BSU_ESCR1
- msr::MSR_C0_PMON_BOX_CTRL
- msr::MSR_C0_PMON_BOX_OVF_CTRL
- msr::MSR_C0_PMON_BOX_STATUS
- msr::MSR_C0_PMON_CTR0
- msr::MSR_C0_PMON_CTR1
- msr::MSR_C0_PMON_CTR2
- msr::MSR_C0_PMON_CTR3
- msr::MSR_C0_PMON_CTR4
- msr::MSR_C0_PMON_CTR5
- msr::MSR_C0_PMON_EVNT_SEL0
- msr::MSR_C0_PMON_EVNT_SEL1
- msr::MSR_C0_PMON_EVNT_SEL2
- msr::MSR_C0_PMON_EVNT_SEL3
- msr::MSR_C0_PMON_EVNT_SEL4
- msr::MSR_C0_PMON_EVNT_SEL5
- msr::MSR_C1_PMON_BOX_CTRL
- msr::MSR_C1_PMON_BOX_OVF_CTRL
- msr::MSR_C1_PMON_BOX_STATUS
- msr::MSR_C1_PMON_CTR0
- msr::MSR_C1_PMON_CTR1
- msr::MSR_C1_PMON_CTR2
- msr::MSR_C1_PMON_CTR3
- msr::MSR_C1_PMON_CTR4
- msr::MSR_C1_PMON_CTR5
- msr::MSR_C1_PMON_EVNT_SEL0
- msr::MSR_C1_PMON_EVNT_SEL1
- msr::MSR_C1_PMON_EVNT_SEL2
- msr::MSR_C1_PMON_EVNT_SEL3
- msr::MSR_C1_PMON_EVNT_SEL4
- msr::MSR_C1_PMON_EVNT_SEL5
- msr::MSR_C2_PMON_BOX_CTRL
- msr::MSR_C2_PMON_BOX_OVF_CTRL
- msr::MSR_C2_PMON_BOX_STATUS
- msr::MSR_C2_PMON_CTR0
- msr::MSR_C2_PMON_CTR1
- msr::MSR_C2_PMON_CTR2
- msr::MSR_C2_PMON_CTR3
- msr::MSR_C2_PMON_CTR4
- msr::MSR_C2_PMON_CTR5
- msr::MSR_C2_PMON_EVNT_SEL0
- msr::MSR_C2_PMON_EVNT_SEL1
- msr::MSR_C2_PMON_EVNT_SEL2
- msr::MSR_C2_PMON_EVNT_SEL3
- msr::MSR_C2_PMON_EVNT_SEL4
- msr::MSR_C2_PMON_EVNT_SEL5
- msr::MSR_C3_PMON_BOX_CTRL
- msr::MSR_C3_PMON_BOX_OVF_CTRL
- msr::MSR_C3_PMON_BOX_STATUS
- msr::MSR_C3_PMON_CTR0
- msr::MSR_C3_PMON_CTR1
- msr::MSR_C3_PMON_CTR2
- msr::MSR_C3_PMON_CTR3
- msr::MSR_C3_PMON_CTR4
- msr::MSR_C3_PMON_CTR5
- msr::MSR_C3_PMON_EVNT_SEL0
- msr::MSR_C3_PMON_EVNT_SEL1
- msr::MSR_C3_PMON_EVNT_SEL2
- msr::MSR_C3_PMON_EVNT_SEL3
- msr::MSR_C3_PMON_EVNT_SEL4
- msr::MSR_C3_PMON_EVNT_SEL5
- msr::MSR_C4_PMON_BOX_CTRL
- msr::MSR_C4_PMON_BOX_OVF_CTRL
- msr::MSR_C4_PMON_BOX_STATUS
- msr::MSR_C4_PMON_CTR0
- msr::MSR_C4_PMON_CTR1
- msr::MSR_C4_PMON_CTR2
- msr::MSR_C4_PMON_CTR3
- msr::MSR_C4_PMON_CTR4
- msr::MSR_C4_PMON_CTR5
- msr::MSR_C4_PMON_EVNT_SEL0
- msr::MSR_C4_PMON_EVNT_SEL1
- msr::MSR_C4_PMON_EVNT_SEL2
- msr::MSR_C4_PMON_EVNT_SEL3
- msr::MSR_C4_PMON_EVNT_SEL4
- msr::MSR_C4_PMON_EVNT_SEL5
- msr::MSR_C5_PMON_BOX_CTRL
- msr::MSR_C5_PMON_BOX_OVF_CTRL
- msr::MSR_C5_PMON_BOX_STATUS
- msr::MSR_C5_PMON_CTR0
- msr::MSR_C5_PMON_CTR1
- msr::MSR_C5_PMON_CTR2
- msr::MSR_C5_PMON_CTR3
- msr::MSR_C5_PMON_CTR4
- msr::MSR_C5_PMON_CTR5
- msr::MSR_C5_PMON_EVNT_SEL0
- msr::MSR_C5_PMON_EVNT_SEL1
- msr::MSR_C5_PMON_EVNT_SEL2
- msr::MSR_C5_PMON_EVNT_SEL3
- msr::MSR_C5_PMON_EVNT_SEL4
- msr::MSR_C5_PMON_EVNT_SEL5
- msr::MSR_C6_PMON_BOX_CTRL
- msr::MSR_C6_PMON_BOX_OVF_CTRL
- msr::MSR_C6_PMON_BOX_STATUS
- msr::MSR_C6_PMON_CTR0
- msr::MSR_C6_PMON_CTR1
- msr::MSR_C6_PMON_CTR2
- msr::MSR_C6_PMON_CTR3
- msr::MSR_C6_PMON_CTR4
- msr::MSR_C6_PMON_CTR5
- msr::MSR_C6_PMON_EVNT_SEL0
- msr::MSR_C6_PMON_EVNT_SEL1
- msr::MSR_C6_PMON_EVNT_SEL2
- msr::MSR_C6_PMON_EVNT_SEL3
- msr::MSR_C6_PMON_EVNT_SEL4
- msr::MSR_C6_PMON_EVNT_SEL5
- msr::MSR_C7_PMON_BOX_CTRL
- msr::MSR_C7_PMON_BOX_OVF_CTRL
- msr::MSR_C7_PMON_BOX_STATUS
- msr::MSR_C7_PMON_CTR0
- msr::MSR_C7_PMON_CTR1
- msr::MSR_C7_PMON_CTR2
- msr::MSR_C7_PMON_CTR3
- msr::MSR_C7_PMON_CTR4
- msr::MSR_C7_PMON_CTR5
- msr::MSR_C7_PMON_EVNT_SEL0
- msr::MSR_C7_PMON_EVNT_SEL1
- msr::MSR_C7_PMON_EVNT_SEL2
- msr::MSR_C7_PMON_EVNT_SEL3
- msr::MSR_C7_PMON_EVNT_SEL4
- msr::MSR_C7_PMON_EVNT_SEL5
- msr::MSR_C8_PMON_BOX_CTRL
- msr::MSR_C8_PMON_BOX_OVF_CTRL
- msr::MSR_C8_PMON_BOX_STATUS
- msr::MSR_C8_PMON_CTR0
- msr::MSR_C8_PMON_CTR1
- msr::MSR_C8_PMON_CTR2
- msr::MSR_C8_PMON_CTR3
- msr::MSR_C8_PMON_CTR4
- msr::MSR_C8_PMON_CTR5
- msr::MSR_C8_PMON_EVNT_SEL0
- msr::MSR_C8_PMON_EVNT_SEL1
- msr::MSR_C8_PMON_EVNT_SEL2
- msr::MSR_C8_PMON_EVNT_SEL3
- msr::MSR_C8_PMON_EVNT_SEL4
- msr::MSR_C8_PMON_EVNT_SEL5
- msr::MSR_C9_PMON_BOX_CTRL
- msr::MSR_C9_PMON_BOX_OVF_CTRL
- msr::MSR_C9_PMON_BOX_STATUS
- msr::MSR_C9_PMON_CTR0
- msr::MSR_C9_PMON_CTR1
- msr::MSR_C9_PMON_CTR2
- msr::MSR_C9_PMON_CTR3
- msr::MSR_C9_PMON_CTR4
- msr::MSR_C9_PMON_CTR5
- msr::MSR_C9_PMON_EVNT_SEL0
- msr::MSR_C9_PMON_EVNT_SEL1
- msr::MSR_C9_PMON_EVNT_SEL2
- msr::MSR_C9_PMON_EVNT_SEL3
- msr::MSR_C9_PMON_EVNT_SEL4
- msr::MSR_C9_PMON_EVNT_SEL5
- msr::MSR_CONFIG_TDP_CONTROL
- msr::MSR_CONFIG_TDP_LEVEL1
- msr::MSR_CONFIG_TDP_LEVEL2
- msr::MSR_CONFIG_TDP_NOMINAL
- msr::MSR_CORE_C1_RESIDENCY
- msr::MSR_CORE_C3_RESIDENCY
- msr::MSR_CORE_C4_RESIDENCY
- msr::MSR_CORE_C6_RESIDENCY
- msr::MSR_CORE_C7_RESIDENCY
- msr::MSR_CRU_ESCR0
- msr::MSR_CRU_ESCR1
- msr::MSR_CRU_ESCR2
- msr::MSR_CRU_ESCR3
- msr::MSR_CRU_ESCR4
- msr::MSR_CRU_ESCR5
- msr::MSR_DAC_ESCR0
- msr::MSR_DAC_ESCR1
- msr::MSR_DEBUGCTLA
- msr::MSR_DEBUGCTLB
- msr::MSR_DRAM_ENERGY_STATUS
- msr::MSR_DRAM_PERF_STATUS
- msr::MSR_DRAM_POWER_INFO
- msr::MSR_DRAM_POWER_LIMIT
- msr::MSR_EBC_FREQUENCY_ID
- msr::MSR_EBC_HARD_POWERON
- msr::MSR_EBC_SOFT_POWERON
- msr::MSR_EBL_CR_POWERON
- msr::MSR_EFSB_DRDY0
- msr::MSR_EFSB_DRDY1
- msr::MSR_EMON_L3_CTR_CTL0
- msr::MSR_EMON_L3_CTR_CTL1
- msr::MSR_EMON_L3_CTR_CTL2
- msr::MSR_EMON_L3_CTR_CTL3
- msr::MSR_EMON_L3_CTR_CTL4
- msr::MSR_EMON_L3_CTR_CTL5
- msr::MSR_EMON_L3_CTR_CTL6
- msr::MSR_EMON_L3_CTR_CTL7
- msr::MSR_EMON_L3_GL_CTL
- msr::MSR_ERROR_CONTROL
- msr::MSR_FIRM_ESCR0
- msr::MSR_FIRM_ESCR1
- msr::MSR_FLAME_CCCR0
- msr::MSR_FLAME_CCCR1
- msr::MSR_FLAME_CCCR2
- msr::MSR_FLAME_CCCR3
- msr::MSR_FLAME_COUNTER0
- msr::MSR_FLAME_COUNTER1
- msr::MSR_FLAME_COUNTER2
- msr::MSR_FLAME_COUNTER3
- msr::MSR_FLAME_ESCR0
- msr::MSR_FLAME_ESCR1
- msr::MSR_FSB_ESCR0
- msr::MSR_FSB_ESCR1
- msr::MSR_FSB_FREQ
- msr::MSR_GQ_SNOOP_MESF
- msr::MSR_IA32_ADDR0_END
- msr::MSR_IA32_ADDR0_START
- msr::MSR_IA32_ADDR1_END
- msr::MSR_IA32_ADDR1_START
- msr::MSR_IA32_ADDR2_END
- msr::MSR_IA32_ADDR2_START
- msr::MSR_IA32_ADDR3_END
- msr::MSR_IA32_ADDR3_START
- msr::MSR_IA32_CR3_MATCH
- msr::MSR_IA32_RTIT_CTL
- msr::MSR_IA32_RTIT_OUTPUT_BASE
- msr::MSR_IA32_RTIT_OUTPUT_MASK_PTRS
- msr::MSR_IA32_RTIT_STATUS
- msr::MSR_IA32_TSX_CTRL
- msr::MSR_IFSB_BUSQ0
- msr::MSR_IFSB_BUSQ1
- msr::MSR_IFSB_CNTR7
- msr::MSR_IFSB_CTL6
- msr::MSR_IFSB_SNPQ0
- msr::MSR_IFSB_SNPQ1
- msr::MSR_IQ_CCCR0
- msr::MSR_IQ_CCCR1
- msr::MSR_IQ_CCCR2
- msr::MSR_IQ_CCCR3
- msr::MSR_IQ_CCCR4
- msr::MSR_IQ_CCCR5
- msr::MSR_IQ_COUNTER4
- msr::MSR_IQ_COUNTER5
- msr::MSR_IQ_ESCR0
- msr::MSR_IQ_ESCR1
- msr::MSR_IS_ESCR0
- msr::MSR_IS_ESCR1
- msr::MSR_ITLB_ESCR0
- msr::MSR_ITLB_ESCR1
- msr::MSR_IX_ESCR0
- msr::MSR_LASTBRANCH_0
- msr::MSR_LASTBRANCH_0_FROM_IP
- msr::MSR_LASTBRANCH_0_TO_IP
- msr::MSR_LASTBRANCH_1
- msr::MSR_LASTBRANCH_10_FROM_IP
- msr::MSR_LASTBRANCH_10_TO_IP
- msr::MSR_LASTBRANCH_11_FROM_IP
- msr::MSR_LASTBRANCH_11_TO_IP
- msr::MSR_LASTBRANCH_12_FROM_IP
- msr::MSR_LASTBRANCH_12_TO_IP
- msr::MSR_LASTBRANCH_13_FROM_IP
- msr::MSR_LASTBRANCH_13_TO_IP
- msr::MSR_LASTBRANCH_14_FROM_IP
- msr::MSR_LASTBRANCH_14_TO_IP
- msr::MSR_LASTBRANCH_15_FROM_IP
- msr::MSR_LASTBRANCH_15_TO_IP
- msr::MSR_LASTBRANCH_1_FROM_IP
- msr::MSR_LASTBRANCH_1_TO_IP
- msr::MSR_LASTBRANCH_2
- msr::MSR_LASTBRANCH_2_FROM_IP
- msr::MSR_LASTBRANCH_2_TO_IP
- msr::MSR_LASTBRANCH_3
- msr::MSR_LASTBRANCH_3_FROM_IP
- msr::MSR_LASTBRANCH_3_TO_IP
- msr::MSR_LASTBRANCH_4
- msr::MSR_LASTBRANCH_4_FROM_IP
- msr::MSR_LASTBRANCH_4_TO_IP
- msr::MSR_LASTBRANCH_5
- msr::MSR_LASTBRANCH_5_FROM_IP
- msr::MSR_LASTBRANCH_5_TO_IP
- msr::MSR_LASTBRANCH_6
- msr::MSR_LASTBRANCH_6_FROM_IP
- msr::MSR_LASTBRANCH_6_TO_IP
- msr::MSR_LASTBRANCH_7
- msr::MSR_LASTBRANCH_7_FROM_IP
- msr::MSR_LASTBRANCH_7_TO_IP
- msr::MSR_LASTBRANCH_8_FROM_IP
- msr::MSR_LASTBRANCH_8_TO_IP
- msr::MSR_LASTBRANCH_9_FROM_IP
- msr::MSR_LASTBRANCH_9_TO_IP
- msr::MSR_LASTBRANCH_TOS
- msr::MSR_LBR_SELECT
- msr::MSR_LER_FROM_LIP
- msr::MSR_LER_TO_LIP
- msr::MSR_M0_PMON_ADDR_MASK
- msr::MSR_M0_PMON_ADDR_MATCH
- msr::MSR_M0_PMON_BOX_CTRL
- msr::MSR_M0_PMON_BOX_OVF_CTRL
- msr::MSR_M0_PMON_BOX_STATUS
- msr::MSR_M0_PMON_CTR0
- msr::MSR_M0_PMON_CTR1
- msr::MSR_M0_PMON_CTR2
- msr::MSR_M0_PMON_CTR3
- msr::MSR_M0_PMON_CTR4
- msr::MSR_M0_PMON_CTR5
- msr::MSR_M0_PMON_DSP
- msr::MSR_M0_PMON_EVNT_SEL0
- msr::MSR_M0_PMON_EVNT_SEL1
- msr::MSR_M0_PMON_EVNT_SEL2
- msr::MSR_M0_PMON_EVNT_SEL3
- msr::MSR_M0_PMON_EVNT_SEL4
- msr::MSR_M0_PMON_EVNT_SEL5
- msr::MSR_M0_PMON_ISS
- msr::MSR_M0_PMON_MAP
- msr::MSR_M0_PMON_MM_CONFIG
- msr::MSR_M0_PMON_MSC_THR
- msr::MSR_M0_PMON_PGT
- msr::MSR_M0_PMON_PLD
- msr::MSR_M0_PMON_TIMESTAMP
- msr::MSR_M0_PMON_ZDP
- msr::MSR_M1_PMON_ADDR_MASK
- msr::MSR_M1_PMON_ADDR_MATCH
- msr::MSR_M1_PMON_BOX_CTRL
- msr::MSR_M1_PMON_BOX_OVF_CTRL
- msr::MSR_M1_PMON_BOX_STATUS
- msr::MSR_M1_PMON_CTR0
- msr::MSR_M1_PMON_CTR1
- msr::MSR_M1_PMON_CTR2
- msr::MSR_M1_PMON_CTR3
- msr::MSR_M1_PMON_CTR4
- msr::MSR_M1_PMON_CTR5
- msr::MSR_M1_PMON_DSP
- msr::MSR_M1_PMON_EVNT_SEL0
- msr::MSR_M1_PMON_EVNT_SEL1
- msr::MSR_M1_PMON_EVNT_SEL2
- msr::MSR_M1_PMON_EVNT_SEL3
- msr::MSR_M1_PMON_EVNT_SEL4
- msr::MSR_M1_PMON_EVNT_SEL5
- msr::MSR_M1_PMON_ISS
- msr::MSR_M1_PMON_MAP
- msr::MSR_M1_PMON_MM_CONFIG
- msr::MSR_M1_PMON_MSC_THR
- msr::MSR_M1_PMON_PGT
- msr::MSR_M1_PMON_PLD
- msr::MSR_M1_PMON_TIMESTAMP
- msr::MSR_M1_PMON_ZDP
- msr::MSR_MC0_MISC
- msr::MSR_MC10_ADDR
- msr::MSR_MC10_CTL
- msr::MSR_MC10_MISC
- msr::MSR_MC10_STATUS
- msr::MSR_MC11_ADDR
- msr::MSR_MC11_CTL
- msr::MSR_MC11_MISC
- msr::MSR_MC11_STATUS
- msr::MSR_MC12_ADDR
- msr::MSR_MC12_CTL
- msr::MSR_MC12_MISC
- msr::MSR_MC12_STATUS
- msr::MSR_MC13_ADDR
- msr::MSR_MC13_CTL
- msr::MSR_MC13_MISC
- msr::MSR_MC13_STATUS
- msr::MSR_MC14_ADDR
- msr::MSR_MC14_CTL
- msr::MSR_MC14_MISC
- msr::MSR_MC14_STATUS
- msr::MSR_MC15_ADDR
- msr::MSR_MC15_CTL
- msr::MSR_MC15_MISC
- msr::MSR_MC15_STATUS
- msr::MSR_MC16_ADDR
- msr::MSR_MC16_CTL
- msr::MSR_MC16_MISC
- msr::MSR_MC16_STATUS
- msr::MSR_MC17_ADDR
- msr::MSR_MC17_CTL
- msr::MSR_MC17_MISC
- msr::MSR_MC17_STATUS
- msr::MSR_MC18_ADDR
- msr::MSR_MC18_CTL
- msr::MSR_MC18_MISC
- msr::MSR_MC18_STATUS
- msr::MSR_MC19_ADDR
- msr::MSR_MC19_CTL
- msr::MSR_MC19_MISC
- msr::MSR_MC19_STATUS
- msr::MSR_MC1_MISC
- msr::MSR_MC20_ADDR
- msr::MSR_MC20_CTL
- msr::MSR_MC20_MISC
- msr::MSR_MC20_STATUS
- msr::MSR_MC21_ADDR
- msr::MSR_MC21_CTL
- msr::MSR_MC21_MISC
- msr::MSR_MC21_STATUS
- msr::MSR_MC22_ADDR
- msr::MSR_MC22_CTL
- msr::MSR_MC22_MISC
- msr::MSR_MC22_STATUS
- msr::MSR_MC23_ADDR
- msr::MSR_MC23_CTL
- msr::MSR_MC23_MISC
- msr::MSR_MC23_STATUS
- msr::MSR_MC24_ADDR
- msr::MSR_MC24_CTL
- msr::MSR_MC24_MISC
- msr::MSR_MC24_STATUS
- msr::MSR_MC25_ADDR
- msr::MSR_MC25_CTL
- msr::MSR_MC25_MISC
- msr::MSR_MC25_STATUS
- msr::MSR_MC26_ADDR
- msr::MSR_MC26_CTL
- msr::MSR_MC26_MISC
- msr::MSR_MC26_STATUS
- msr::MSR_MC2_MISC
- msr::MSR_MC3_ADDR
- msr::MSR_MC3_CTL
- msr::MSR_MC3_MISC
- msr::MSR_MC3_STATUS
- msr::MSR_MC4_ADDR
- msr::MSR_MC4_CTL
- msr::MSR_MC4_CTL2
- msr::MSR_MC4_MISC
- msr::MSR_MC4_STATUS
- msr::MSR_MC5_ADDR
- msr::MSR_MC5_CTL
- msr::MSR_MC5_MISC
- msr::MSR_MC5_STATUS
- msr::MSR_MC6_ADDR
- msr::MSR_MC6_CTL
- msr::MSR_MC6_MISC
- msr::MSR_MC6_STATUS
- msr::MSR_MC7_ADDR
- msr::MSR_MC7_CTL
- msr::MSR_MC7_MISC
- msr::MSR_MC7_STATUS
- msr::MSR_MC8_ADDR
- msr::MSR_MC8_CTL
- msr::MSR_MC8_MISC
- msr::MSR_MC8_STATUS
- msr::MSR_MC9_ADDR
- msr::MSR_MC9_CTL
- msr::MSR_MC9_MISC
- msr::MSR_MC9_STATUS
- msr::MSR_MCG_MISC
- msr::MSR_MCG_R10
- msr::MSR_MCG_R11
- msr::MSR_MCG_R12
- msr::MSR_MCG_R13
- msr::MSR_MCG_R14
- msr::MSR_MCG_R8
- msr::MSR_MCG_R9
- msr::MSR_MCG_RAX
- msr::MSR_MCG_RBP
- msr::MSR_MCG_RBX
- msr::MSR_MCG_RCX
- msr::MSR_MCG_RDI
- msr::MSR_MCG_RDX
- msr::MSR_MCG_RFLAGS
- msr::MSR_MCG_RIP
- msr::MSR_MCG_RSI
- msr::MSR_MISC_PWR_MGMT
- msr::MSR_MOB_ESCR0
- msr::MSR_MOB_ESCR1
- msr::MSR_MS_CCCR0
- msr::MSR_MS_CCCR1
- msr::MSR_MS_CCCR2
- msr::MSR_MS_CCCR3
- msr::MSR_MS_COUNTER0
- msr::MSR_MS_COUNTER1
- msr::MSR_MS_COUNTER2
- msr::MSR_MS_COUNTER3
- msr::MSR_MS_ESCR0
- msr::MSR_MS_ESCR1
- msr::MSR_OFFCORE_RSP_0
- msr::MSR_OFFCORE_RSP_1
- msr::MSR_PEBS_ENABLE
- msr::MSR_PEBS_LD_LAT
- msr::MSR_PEBS_MATRIX_VERT
- msr::MSR_PEBS_NUM_ALT
- msr::MSR_PERF_CAPABILITIES
- msr::MSR_PERF_FIXED_CTR0
- msr::MSR_PERF_FIXED_CTR1
- msr::MSR_PERF_FIXED_CTR2
- msr::MSR_PERF_FIXED_CTR_CTRL
- msr::MSR_PERF_GLOBAL_CTRL
- msr::MSR_PERF_GLOBAL_OVF_CTRL
- msr::MSR_PERF_GLOBAL_STAUS
- msr::MSR_PERF_STATUS
- msr::MSR_PKGC3_IRTL
- msr::MSR_PKGC6_IRTL
- msr::MSR_PKGC7_IRTL
- msr::MSR_PKG_C10_RESIDENCY
- msr::MSR_PKG_C2_RESIDENCY
- msr::MSR_PKG_C3_RESIDENCY
- msr::MSR_PKG_C4_RESIDENCY
- msr::MSR_PKG_C6C_RESIDENCY
- msr::MSR_PKG_C6_RESIDENCY
- msr::MSR_PKG_C7_RESIDENCY
- msr::MSR_PKG_C9_RESIDENCY
- msr::MSR_PKG_CST_CONFIG_CONTROL
- msr::MSR_PKG_ENERGY_STATUS
- msr::MSR_PKG_PERF_STATUS
- msr::MSR_PKG_POWER_INFO
- msr::MSR_PKG_POWER_LIMIT
- msr::MSR_PLATFORM_BRV
- msr::MSR_PLATFORM_ID
- msr::MSR_PLATFORM_INFO
- msr::MSR_PMG_IO_CAPTURE_BASE
- msr::MSR_PMH_ESCR0
- msr::MSR_PMH_ESCR1
- msr::MSR_POWER_CTL
- msr::MSR_PP0_ENERGY_STATUS
- msr::MSR_PP0_PERF_STATUS
- msr::MSR_PP0_POLICY
- msr::MSR_PP0_POWER_LIMIT
- msr::MSR_PP1_ENERGY_STATUS
- msr::MSR_PP1_POLICY
- msr::MSR_PP1_POWER_LIMIT
- msr::MSR_R0_PMON_BOX_CTRL
- msr::MSR_R0_PMON_BOX_OVF_CTRL
- msr::MSR_R0_PMON_BOX_STATUS
- msr::MSR_R0_PMON_CTR0
- msr::MSR_R0_PMON_CTR1
- msr::MSR_R0_PMON_CTR2
- msr::MSR_R0_PMON_CTR3
- msr::MSR_R0_PMON_CTR4
- msr::MSR_R0_PMON_CTR5
- msr::MSR_R0_PMON_CTR6
- msr::MSR_R0_PMON_CTR7
- msr::MSR_R0_PMON_EVNT_SEL0
- msr::MSR_R0_PMON_EVNT_SEL1
- msr::MSR_R0_PMON_EVNT_SEL2
- msr::MSR_R0_PMON_EVNT_SEL3
- msr::MSR_R0_PMON_EVNT_SEL4
- msr::MSR_R0_PMON_EVNT_SEL5
- msr::MSR_R0_PMON_EVNT_SEL6
- msr::MSR_R0_PMON_EVNT_SEL7
- msr::MSR_R0_PMON_IPERF0_P0
- msr::MSR_R0_PMON_IPERF0_P1
- msr::MSR_R0_PMON_IPERF0_P2
- msr::MSR_R0_PMON_IPERF0_P3
- msr::MSR_R0_PMON_IPERF0_P4
- msr::MSR_R0_PMON_IPERF0_P5
- msr::MSR_R0_PMON_IPERF0_P6
- msr::MSR_R0_PMON_IPERF0_P7
- msr::MSR_R0_PMON_QLX_P0
- msr::MSR_R0_PMON_QLX_P1
- msr::MSR_R0_PMON_QLX_P2
- msr::MSR_R0_PMON_QLX_P3
- msr::MSR_R1_PMON_BOX_CTRL
- msr::MSR_R1_PMON_BOX_OVF_CTRL
- msr::MSR_R1_PMON_BOX_STATUS
- msr::MSR_R1_PMON_CTR10
- msr::MSR_R1_PMON_CTR11
- msr::MSR_R1_PMON_CTR12
- msr::MSR_R1_PMON_CTR13
- msr::MSR_R1_PMON_CTR14
- msr::MSR_R1_PMON_CTR15
- msr::MSR_R1_PMON_CTR8
- msr::MSR_R1_PMON_CTR9
- msr::MSR_R1_PMON_EVNT_SEL10
- msr::MSR_R1_PMON_EVNT_SEL11
- msr::MSR_R1_PMON_EVNT_SEL12
- msr::MSR_R1_PMON_EVNT_SEL13
- msr::MSR_R1_PMON_EVNT_SEL14
- msr::MSR_R1_PMON_EVNT_SEL15
- msr::MSR_R1_PMON_EVNT_SEL8
- msr::MSR_R1_PMON_EVNT_SEL9
- msr::MSR_R1_PMON_IPERF1_P10
- msr::MSR_R1_PMON_IPERF1_P11
- msr::MSR_R1_PMON_IPERF1_P12
- msr::MSR_R1_PMON_IPERF1_P13
- msr::MSR_R1_PMON_IPERF1_P14
- msr::MSR_R1_PMON_IPERF1_P15
- msr::MSR_R1_PMON_IPERF1_P8
- msr::MSR_R1_PMON_IPERF1_P9
- msr::MSR_R1_PMON_QLX_P4
- msr::MSR_R1_PMON_QLX_P5
- msr::MSR_R1_PMON_QLX_P6
- msr::MSR_R1_PMON_QLX_P7
- msr::MSR_RAPL_POWER_UNIT
- msr::MSR_RAT_ESCR0
- msr::MSR_RAT_ESCR1
- msr::MSR_S0_PMON_BOX_CTRL
- msr::MSR_S0_PMON_BOX_OVF_CTRL
- msr::MSR_S0_PMON_BOX_STATUS
- msr::MSR_S0_PMON_CTR0
- msr::MSR_S0_PMON_CTR1
- msr::MSR_S0_PMON_CTR2
- msr::MSR_S0_PMON_CTR3
- msr::MSR_S0_PMON_EVNT_SEL0
- msr::MSR_S0_PMON_EVNT_SEL1
- msr::MSR_S0_PMON_EVNT_SEL2
- msr::MSR_S0_PMON_EVNT_SEL3
- msr::MSR_S0_PMON_MASK
- msr::MSR_S0_PMON_MATCH
- msr::MSR_S1_PMON_BOX_CTRL
- msr::MSR_S1_PMON_BOX_OVF_CTRL
- msr::MSR_S1_PMON_BOX_STATUS
- msr::MSR_S1_PMON_CTR0
- msr::MSR_S1_PMON_CTR1
- msr::MSR_S1_PMON_CTR2
- msr::MSR_S1_PMON_CTR3
- msr::MSR_S1_PMON_EVNT_SEL0
- msr::MSR_S1_PMON_EVNT_SEL1
- msr::MSR_S1_PMON_EVNT_SEL2
- msr::MSR_S1_PMON_EVNT_SEL3
- msr::MSR_S1_PMON_MASK
- msr::MSR_S1_PMON_MATCH
- msr::MSR_SAAT_ESCR0
- msr::MSR_SAAT_ESCR1
- msr::MSR_SMI_COUNT
- msr::MSR_SMM_BLOCKED
- msr::MSR_SMM_DELAYED
- msr::MSR_SMM_FEATURE_CONTROL
- msr::MSR_SMM_MCA_CAP
- msr::MSR_SMRR_PHYSMASK
- msr::MSR_SSU_ESCR0
- msr::MSR_TBPU_ESCR0
- msr::MSR_TBPU_ESCR1
- msr::MSR_TC_ESCR0
- msr::MSR_TC_ESCR1
- msr::MSR_TEMPERATURE_TARGET
- msr::MSR_THERM2_CTL
- msr::MSR_TURBO_ACTIVATION_RATIO
- msr::MSR_TURBO_POWER_CURRENT_LIMIT
- msr::MSR_TURBO_RATIO_LIMIT
- msr::MSR_U2L_ESCR0
- msr::MSR_U2L_ESCR1
- msr::MSR_UNCORE_ADDR_OPCODE_MATCH
- msr::MSR_UNCORE_FIXED_CTR0
- msr::MSR_UNCORE_FIXED_CTR_CTRL
- msr::MSR_UNCORE_PERFEVTSEL0
- msr::MSR_UNCORE_PERFEVTSEL1
- msr::MSR_UNCORE_PERFEVTSEL2
- msr::MSR_UNCORE_PERFEVTSEL3
- msr::MSR_UNCORE_PERFEVTSEL4
- msr::MSR_UNCORE_PERFEVTSEL5
- msr::MSR_UNCORE_PERFEVTSEL6
- msr::MSR_UNCORE_PERFEVTSEL7
- msr::MSR_UNCORE_PERF_GLOBAL_CTRL
- msr::MSR_UNCORE_PERF_GLOBAL_OVF_CTRL
- msr::MSR_UNCORE_PERF_GLOBAL_STATUS
- msr::MSR_UNCORE_PMC0
- msr::MSR_UNCORE_PMC1
- msr::MSR_UNCORE_PMC2
- msr::MSR_UNCORE_PMC3
- msr::MSR_UNCORE_PMC4
- msr::MSR_UNCORE_PMC5
- msr::MSR_UNCORE_PMC6
- msr::MSR_UNCORE_PMC7
- msr::MSR_UNC_ARB_PERFEVTSEL0
- msr::MSR_UNC_ARB_PERFEVTSEL1
- msr::MSR_UNC_ARB_PER_CTR0
- msr::MSR_UNC_ARB_PER_CTR1
- msr::MSR_UNC_CBO_0_PERFEVTSEL0
- msr::MSR_UNC_CBO_0_PERFEVTSEL1
- msr::MSR_UNC_CBO_0_PER_CTR0
- msr::MSR_UNC_CBO_0_PER_CTR1
- msr::MSR_UNC_CBO_1_PERFEVTSEL0
- msr::MSR_UNC_CBO_1_PERFEVTSEL1
- msr::MSR_UNC_CBO_1_PER_CTR0
- msr::MSR_UNC_CBO_1_PER_CTR1
- msr::MSR_UNC_CBO_2_PERFEVTSEL0
- msr::MSR_UNC_CBO_2_PERFEVTSEL1
- msr::MSR_UNC_CBO_2_PER_CTR0
- msr::MSR_UNC_CBO_2_PER_CTR1
- msr::MSR_UNC_CBO_3_PERFEVTSEL0
- msr::MSR_UNC_CBO_3_PERFEVTSEL1
- msr::MSR_UNC_CBO_3_PER_CTR0
- msr::MSR_UNC_CBO_3_PER_CTR1
- msr::MSR_UNC_CBO_CONFIG
- msr::MSR_UNC_PERF_FIXED_CTR
- msr::MSR_UNC_PERF_FIXED_CTRL
- msr::MSR_UNC_PERF_GLOBAL_CTRL
- msr::MSR_UNC_PERF_GLOBAL_STATUS
- msr::MSR_U_PMON_CTR
- msr::MSR_U_PMON_EVNT_SEL
- msr::MSR_U_PMON_GLOBAL_CTRL
- msr::MSR_U_PMON_GLOBAL_OVF_CTRL
- msr::MSR_U_PMON_GLOBAL_STATUS
- msr::MSR_W_PMON_BOX_CTRL
- msr::MSR_W_PMON_BOX_OVF_CTRL
- msr::MSR_W_PMON_BOX_STATUS
- msr::MSR_W_PMON_CTR0
- msr::MSR_W_PMON_CTR1
- msr::MSR_W_PMON_CTR2
- msr::MSR_W_PMON_CTR3
- msr::MSR_W_PMON_EVNT_SEL0
- msr::MSR_W_PMON_EVNT_SEL1
- msr::MSR_W_PMON_EVNT_SEL2
- msr::MSR_W_PMON_EVNT_SEL3
- msr::MSR_W_PMON_FIXED_CTR
- msr::MSR_W_PMON_FIXED_CTR_CTL
- msr::P5_MC_ADDR
- msr::P5_MC_TYPE
- msr::ROB_CR_BKUPTMPDR6
- msr::SYSENTER_CS_MSR
- msr::SYSENTER_EIP_MSR
- msr::SYSENTER_ESP_MSR
- msr::TEST_CTL
- msr::TSC
- vmx::vmcs::control::APIC_ACCESS_ADDR_FULL
- vmx::vmcs::control::APIC_ACCESS_ADDR_HIGH
- vmx::vmcs::control::CR0_GUEST_HOST_MASK
- vmx::vmcs::control::CR0_READ_SHADOW
- vmx::vmcs::control::CR3_TARGET_COUNT
- vmx::vmcs::control::CR3_TARGET_VALUE0
- vmx::vmcs::control::CR3_TARGET_VALUE1
- vmx::vmcs::control::CR3_TARGET_VALUE2
- vmx::vmcs::control::CR3_TARGET_VALUE3
- vmx::vmcs::control::CR4_GUEST_HOST_MASK
- vmx::vmcs::control::CR4_READ_SHADOW
- vmx::vmcs::control::ENCLS_EXITING_BITMAP_FULL
- vmx::vmcs::control::ENCLS_EXITING_BITMAP_HIGH
- vmx::vmcs::control::EOI_EXIT0_FULL
- vmx::vmcs::control::EOI_EXIT0_HIGH
- vmx::vmcs::control::EOI_EXIT1_FULL
- vmx::vmcs::control::EOI_EXIT1_HIGH
- vmx::vmcs::control::EOI_EXIT2_FULL
- vmx::vmcs::control::EOI_EXIT2_HIGH
- vmx::vmcs::control::EOI_EXIT3_FULL
- vmx::vmcs::control::EOI_EXIT3_HIGH
- vmx::vmcs::control::EPTP_FULL
- vmx::vmcs::control::EPTP_HIGH
- vmx::vmcs::control::EPTP_INDEX
- vmx::vmcs::control::EPTP_LIST_ADDR_FULL
- vmx::vmcs::control::EPTP_LIST_ADDR_HIGH
- vmx::vmcs::control::EXCEPTION_BITMAP
- vmx::vmcs::control::EXECUTIVE_VMCS_PTR_FULL
- vmx::vmcs::control::EXECUTIVE_VMCS_PTR_HIGH
- vmx::vmcs::control::IO_BITMAP_A_ADDR_FULL
- vmx::vmcs::control::IO_BITMAP_A_ADDR_HIGH
- vmx::vmcs::control::IO_BITMAP_B_ADDR_FULL
- vmx::vmcs::control::IO_BITMAP_B_ADDR_HIGH
- vmx::vmcs::control::MSR_BITMAPS_ADDR_FULL
- vmx::vmcs::control::MSR_BITMAPS_ADDR_HIGH
- vmx::vmcs::control::PAGE_FAULT_ERR_CODE_MASK
- vmx::vmcs::control::PAGE_FAULT_ERR_CODE_MATCH
- vmx::vmcs::control::PINBASED_EXEC_CONTROLS
- vmx::vmcs::control::PLE_GAP
- vmx::vmcs::control::PLE_WINDOW
- vmx::vmcs::control::PML_ADDR_FULL
- vmx::vmcs::control::PML_ADDR_HIGH
- vmx::vmcs::control::POSTED_INTERRUPT_DESC_ADDR_FULL
- vmx::vmcs::control::POSTED_INTERRUPT_DESC_ADDR_HIGH
- vmx::vmcs::control::POSTED_INTERRUPT_NOTIFICATION_VECTOR
- vmx::vmcs::control::PRIMARY_PROCBASED_EXEC_CONTROLS
- vmx::vmcs::control::SECONDARY_PROCBASED_EXEC_CONTROLS
- vmx::vmcs::control::SUBPAGE_PERM_TABLE_PTR_FULL
- vmx::vmcs::control::SUBPAGE_PERM_TABLE_PTR_HIGH
- vmx::vmcs::control::TPR_THRESHOLD
- vmx::vmcs::control::TSC_MULTIPLIER_FULL
- vmx::vmcs::control::TSC_MULTIPLIER_HIGH
- vmx::vmcs::control::TSC_OFFSET_FULL
- vmx::vmcs::control::TSC_OFFSET_HIGH
- vmx::vmcs::control::VIRT_APIC_ADDR_FULL
- vmx::vmcs::control::VIRT_APIC_ADDR_HIGH
- vmx::vmcs::control::VIRT_EXCEPTION_INFO_ADDR_FULL
- vmx::vmcs::control::VIRT_EXCEPTION_INFO_ADDR_HIGH
- vmx::vmcs::control::VMENTRY_CONTROLS
- vmx::vmcs::control::VMENTRY_EXCEPTION_ERR_CODE
- vmx::vmcs::control::VMENTRY_INSTRUCTION_LEN
- vmx::vmcs::control::VMENTRY_INTERRUPTION_INFO_FIELD
- vmx::vmcs::control::VMENTRY_MSR_LOAD_ADDR_FULL
- vmx::vmcs::control::VMENTRY_MSR_LOAD_ADDR_HIGH
- vmx::vmcs::control::VMENTRY_MSR_LOAD_COUNT
- vmx::vmcs::control::VMEXIT_CONTROLS
- vmx::vmcs::control::VMEXIT_MSR_LOAD_ADDR_FULL
- vmx::vmcs::control::VMEXIT_MSR_LOAD_ADDR_HIGH
- vmx::vmcs::control::VMEXIT_MSR_LOAD_COUNT
- vmx::vmcs::control::VMEXIT_MSR_STORE_ADDR_FULL
- vmx::vmcs::control::VMEXIT_MSR_STORE_ADDR_HIGH
- vmx::vmcs::control::VMEXIT_MSR_STORE_COUNT
- vmx::vmcs::control::VMREAD_BITMAP_ADDR_FULL
- vmx::vmcs::control::VMREAD_BITMAP_ADDR_HIGH
- vmx::vmcs::control::VMWRITE_BITMAP_ADDR_FULL
- vmx::vmcs::control::VMWRITE_BITMAP_ADDR_HIGH
- vmx::vmcs::control::VM_FUNCTION_CONTROLS_FULL
- vmx::vmcs::control::VM_FUNCTION_CONTROLS_HIGH
- vmx::vmcs::control::VPID
- vmx::vmcs::control::XSS_EXITING_BITMAP_FULL
- vmx::vmcs::control::XSS_EXITING_BITMAP_HIGH
- vmx::vmcs::guest::ACTIVITY_STATE
- vmx::vmcs::guest::CR0
- vmx::vmcs::guest::CR3
- vmx::vmcs::guest::CR4
- vmx::vmcs::guest::CS_ACCESS_RIGHTS
- vmx::vmcs::guest::CS_BASE
- vmx::vmcs::guest::CS_LIMIT
- vmx::vmcs::guest::CS_SELECTOR
- vmx::vmcs::guest::DR7
- vmx::vmcs::guest::DS_ACCESS_RIGHTS
- vmx::vmcs::guest::DS_BASE
- vmx::vmcs::guest::DS_LIMIT
- vmx::vmcs::guest::DS_SELECTOR
- vmx::vmcs::guest::ES_ACCESS_RIGHTS
- vmx::vmcs::guest::ES_BASE
- vmx::vmcs::guest::ES_LIMIT
- vmx::vmcs::guest::ES_SELECTOR
- vmx::vmcs::guest::FS_ACCESS_RIGHTS
- vmx::vmcs::guest::FS_BASE
- vmx::vmcs::guest::FS_LIMIT
- vmx::vmcs::guest::FS_SELECTOR
- vmx::vmcs::guest::GDTR_BASE
- vmx::vmcs::guest::GDTR_LIMIT
- vmx::vmcs::guest::GS_ACCESS_RIGHTS
- vmx::vmcs::guest::GS_BASE
- vmx::vmcs::guest::GS_LIMIT
- vmx::vmcs::guest::GS_SELECTOR
- vmx::vmcs::guest::IA32_BNDCFGS_FULL
- vmx::vmcs::guest::IA32_BNDCFGS_HIGH
- vmx::vmcs::guest::IA32_DEBUGCTL_FULL
- vmx::vmcs::guest::IA32_DEBUGCTL_HIGH
- vmx::vmcs::guest::IA32_EFER_FULL
- vmx::vmcs::guest::IA32_EFER_HIGH
- vmx::vmcs::guest::IA32_PAT_FULL
- vmx::vmcs::guest::IA32_PAT_HIGH
- vmx::vmcs::guest::IA32_PERF_GLOBAL_CTRL_FULL
- vmx::vmcs::guest::IA32_PERF_GLOBAL_CTRL_HIGH
- vmx::vmcs::guest::IA32_RTIT_CTL_FULL
- vmx::vmcs::guest::IA32_RTIT_CTL_HIGH
- vmx::vmcs::guest::IA32_SYSENTER_CS
- vmx::vmcs::guest::IA32_SYSENTER_EIP
- vmx::vmcs::guest::IA32_SYSENTER_ESP
- vmx::vmcs::guest::IDTR_BASE
- vmx::vmcs::guest::IDTR_LIMIT
- vmx::vmcs::guest::INTERRUPTIBILITY_STATE
- vmx::vmcs::guest::INTERRUPT_STATUS
- vmx::vmcs::guest::LDTR_ACCESS_RIGHTS
- vmx::vmcs::guest::LDTR_BASE
- vmx::vmcs::guest::LDTR_LIMIT
- vmx::vmcs::guest::LDTR_SELECTOR
- vmx::vmcs::guest::LINK_PTR_FULL
- vmx::vmcs::guest::LINK_PTR_HIGH
- vmx::vmcs::guest::PDPTE0_FULL
- vmx::vmcs::guest::PDPTE0_HIGH
- vmx::vmcs::guest::PDPTE1_FULL
- vmx::vmcs::guest::PDPTE1_HIGH
- vmx::vmcs::guest::PDPTE2_FULL
- vmx::vmcs::guest::PDPTE2_HIGH
- vmx::vmcs::guest::PDPTE3_FULL
- vmx::vmcs::guest::PDPTE3_HIGH
- vmx::vmcs::guest::PENDING_DBG_EXCEPTIONS
- vmx::vmcs::guest::PML_INDEX
- vmx::vmcs::guest::RFLAGS
- vmx::vmcs::guest::RIP
- vmx::vmcs::guest::RSP
- vmx::vmcs::guest::SMBASE
- vmx::vmcs::guest::SS_ACCESS_RIGHTS
- vmx::vmcs::guest::SS_BASE
- vmx::vmcs::guest::SS_LIMIT
- vmx::vmcs::guest::SS_SELECTOR
- vmx::vmcs::guest::TR_ACCESS_RIGHTS
- vmx::vmcs::guest::TR_BASE
- vmx::vmcs::guest::TR_LIMIT
- vmx::vmcs::guest::TR_SELECTOR
- vmx::vmcs::guest::VMX_PREEMPTION_TIMER_VALUE
- vmx::vmcs::host::CR0
- vmx::vmcs::host::CR3
- vmx::vmcs::host::CR4
- vmx::vmcs::host::CS_SELECTOR
- vmx::vmcs::host::DS_SELECTOR
- vmx::vmcs::host::ES_SELECTOR
- vmx::vmcs::host::FS_BASE
- vmx::vmcs::host::FS_SELECTOR
- vmx::vmcs::host::GDTR_BASE
- vmx::vmcs::host::GS_BASE
- vmx::vmcs::host::GS_SELECTOR
- vmx::vmcs::host::IA32_EFER_FULL
- vmx::vmcs::host::IA32_EFER_HIGH
- vmx::vmcs::host::IA32_PAT_FULL
- vmx::vmcs::host::IA32_PAT_HIGH
- vmx::vmcs::host::IA32_PERF_GLOBAL_CTRL_FULL
- vmx::vmcs::host::IA32_PERF_GLOBAL_CTRL_HIGH
- vmx::vmcs::host::IA32_SYSENTER_CS
- vmx::vmcs::host::IA32_SYSENTER_EIP
- vmx::vmcs::host::IA32_SYSENTER_ESP
- vmx::vmcs::host::IDTR_BASE
- vmx::vmcs::host::RIP
- vmx::vmcs::host::RSP
- vmx::vmcs::host::SS_SELECTOR
- vmx::vmcs::host::TR_BASE
- vmx::vmcs::host::TR_SELECTOR
- vmx::vmcs::ro::EXIT_QUALIFICATION
- vmx::vmcs::ro::EXIT_REASON
- vmx::vmcs::ro::GUEST_LINEAR_ADDR
- vmx::vmcs::ro::GUEST_PHYSICAL_ADDR_FULL
- vmx::vmcs::ro::GUEST_PHYSICAL_ADDR_HIGH
- vmx::vmcs::ro::IDT_VECTORING_ERR_CODE
- vmx::vmcs::ro::IDT_VECTORING_INFO
- vmx::vmcs::ro::IO_RCX
- vmx::vmcs::ro::IO_RDI
- vmx::vmcs::ro::IO_RIP
- vmx::vmcs::ro::IO_RSI
- vmx::vmcs::ro::VMEXIT_INSTRUCTION_INFO
- vmx::vmcs::ro::VMEXIT_INSTRUCTION_LEN
- vmx::vmcs::ro::VMEXIT_INTERRUPTION_ERR_CODE
- vmx::vmcs::ro::VMEXIT_INTERRUPTION_INFO
- vmx::vmcs::ro::VM_INSTRUCTION_ERROR