Expand description
MSR value list and function to read and write them.
Constants
Section 10.4.4, Local APIC Status and Location.
BIOS Update Trigger Register.
Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
Actual Performance Frequency Clock Count (RW) See Table 35-2.
APIC Location and Status (R/W) See Table 35-2. See Section 10.4.4, Local APIC Status and Location.
(If CPUID.0AH: EAX[15:8] > 0) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 1) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 2) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 3) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 4) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 5) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 6) & IA32_PERF_CAPABILITIES[ 13] = 1
(If CPUID.0AH: EAX[15:8] > 7) & IA32_PERF_CAPABILITIES[ 13] = 1
BIOS Update Signature ID (R/W) See Table 35-2.
BIOS Update Trigger Register (W) See Table 35-2.
Clock Modulation (R/W) See Table 35-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
System Call Target Address the compatibility mode.
06_2EH
Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section.
DS Save Area (R/W) See Table 35-2. Points to the DS buffer management area, which is used to manage the BTS and PEBS buffers. See Section 18.12.4, Debug Store (DS) Mechanism.
If ( CPUID.80000001.EDX.[bit 20] or CPUID.80000001.EDX.[bit 29])
if CPUID.6H:ECX[3] = 1
Control Features in IA-32 Processor (R/W) See Table 35-2 (If CPUID.01H:ECX.[bit 5])
Fixed-Function Performance Counter Register 0 (R/W) See Table 35-2.
Fixed-Function Performance Counter Register 1 (R/W) See Table 35-2.
Fixed-Function Performance Counter Register 2 (R/W) See Table 35-2.
Fixed-Function-Counter Control Register (R/W) See Table 35-2.
System Call Flag Mask (R/W) See Table 35-2.
Map of BASE Address of FS (R/W) See Table 35-2.
Map of BASE Address of GS (R/W) See Table 35-2.
Swap Target of BASE Address of GS (R/W) See Table 35-2.
IA-32e Mode System Call Target Address (R/W) See Table 35-2.
See Section 14.3.2.3., IA32_MCi_ADDR MSRs . The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
P6 Family Processors
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Table 35-2.
See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC0_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
P6 Family Processors
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Table 35-2.
See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC1_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
P6 Family Processors
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Table 35-2.
See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
P6 Family Processors
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Table 35-2.
See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC3_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
P6 Family Processors
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Table 35-2.
See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
06_0FH
06_0FH
See Table 35-2.
06_0FH
06_0FH
06_1DH
06_1DH
See Table 35-2.
Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4
06_1DH
06_1AH
06_1AH
See Table 35-2.
06_1AH
06_1AH
06_1AH
06_1AH
See Table 35-2.
06_1AH
06_1AH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
06_2EH
06_2EH
See Table 35-2.
06_2EH
06_2EH
Machine Check Capabilities (R) See Table 35-2. See Section 15.3.1.1, IA32_MCG_CAP MSR.
Machine Check Feature Enable (R/W) See Table 35-2. See Section 15.3.1.3, IA32_MCG_CTL MSR.
Machine Check Status. (R) See Table 35-2. See Section 15.3.1.2, IA32_MCG_STATUS MSR.
See Section 8.10.5, Monitor/Mwait Address Range Determination.
See Section 8.10.5, Monitor/Mwait Address Range Determination, and see Table 35-2.
Maximum Performance Frequency Clock Count (RW) See Table 35-2.
MTRR Information See Section 11.11.1, MTRR Feature Identification. .
Default Memory Types (R/W) Sets the memory type for the regions of physical memory that are not mapped by the MTRRs. See Section 11.11.2.1, IA32_MTRR_DEF_TYPE MSR.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
Variable Range Base MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
if IA32_MTRR_CAP[7:0] > 8
if IA32_MTRR_CAP[7:0] > 9
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs .
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
if IA32_MTRR_CAP[7:0] > 8
if IA32_MTRR_CAP[7:0] > 9
See Section 35.16, MSRs in Pentium Processors.
See Section 35.16, MSRs in Pentium Processors.
If CPUID.06H: EAX[6] = 1
If CPUID.06H: EAX[6] = 1
Page Attribute Table See Section 11.11.2.2, Fixed Range MTRRs.
Performance Event Select for Counter 0 (R/W) Supports all fields described inTable 35-2 and the fields below.
Performance Event Select for Counter 1 (R/W) Supports all fields described inTable 35-2 and the fields below.
Performance Event Select for Counter 2 (R/W) Supports all fields described inTable 35-2 and the fields below.
Performance Event Select for Counter 3 (R/W) Supports all fields described inTable 35-2 and the fields below.
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
See Table 35-2. See Section 17.4.1, IA32_DEBUGCTL MSR.
See Table 35-2. See Section 14.1, Enhanced Intel Speedstep® Technology.
See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.
See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.
See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.
See Table 35-2. See Section 14.1, Enhanced Intel Speedstep® Technology.
06_0FH
Platform ID (R) See Table 35-2. The operating system can use this MSR to determine slot information for the processor and the proper microcode update to load.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
Performance Counter Register See Table 35-2.
If ( CPUID.(EAX=07H, ECX=0):EBX.[bit 12] = 1 )
If ( CPUID.(EAX=07H, ECX=0):EBX.[bit 12] = 1 )
If ( CPUID.(EAX=07H, ECX=0):EBX.[bit 12] = 1 )
If IA32_VMX_MISC[bit 15])
SMM Monitor Configuration (R/W) See Table 35-2.
See Table 35-2.
If IA32_MTRR_CAP[SMRR] = 1
System Call Target Address (R/W) See Table 35-2.
CS register target for CPL 0 code (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.
CPL 0 code entry point (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.
Stack pointer for CPL 0 stack (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.
Thermal Interrupt Control (R/W) See Section 14.5.2, Thermal Monitor, and see Table 35-2.
Thermal Monitor Status (R/W) See Section 14.5.2, Thermal Monitor, and see Table 35-2.
See Section 17.13, Time-Stamp Counter, and see Table 35-2.
Per-Logical-Processor TSC ADJUST (R/W) See Table 35-2.
AUXILIARY TSC Signature. (R/W) See Table 35-2 and Section 17.13.2, IA32_TSC_AUX Register and RDTSCP Support.
TSC Target of Local APIC s TSC Deadline Mode (R/W) See Table 35-2
Reporting Register of Basic VMX Capabilities (R/O) See Table 35-2. See Appendix A.1, Basic VMX Information (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, VMX-Fixed Bits in CR0 (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, VMX-Fixed Bits in CR0 (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, VMX-Fixed Bits in CR4 (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, VMX-Fixed Bits in CR4 (If CPUID.01H:ECX.[bit 9])
If CPUID.01H:ECX.[bit 5] = 1
If CPUID.01H:ECX.[bit 5] = 1
Capability Reporting Register of VM-entry Controls (R/O) See Appendix A.5, VM-Entry Controls (If CPUID.01H:ECX.[bit 9])
If ( CPUID.01H:ECX.[bit 5], IA32_VMX_PROCBASED_C TLS[bit 63], and either IA32_VMX_PROCBASED_C TLS2[bit 33] or IA32_VMX_PROCBASED_C TLS2[bit 37])
Capability Reporting Register of EPT and VPID (R/O) See Table 35-2
Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, VM-Exit Controls (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of VM-function Controls (R/O) See Table 35-2
Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, Miscellaneous Data (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of Pin-based VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of Primary Processor-based VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9])
Capability Reporting Register of Secondary Processor-based VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9] and IA32_VMX_PROCBASED_CTLS[bit 63])
Capability Reporting Register of VM-entry Flex Controls (R/O) See Table 35-2
Capability Reporting Register of VM-exit Flex Controls (R/O) See Table 35-2
Capability Reporting Register of Pin-based VM-execution Flex Controls (R/O) See Table 35-2
Capability Reporting Register of Primary Processor-based VM-execution Flex Controls (R/O) See Table 35-2
Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix A.9, VMCS Enumeration (If CPUID.01H:ECX.[bit 9])
If( CPUID.01H:ECX.[bit 5] = 1 and IA32_VMX_BASIC[bit 55] )
x2APIC ID register (R/O) See x2APIC Specification.
x2APIC Current Count register (R/O)
x2APIC Divide Configuration register (R/W)
x2APIC End of Interrupt. If ( CPUID.01H:ECX.[bit 21] = 1 )
Error Status Register. If ( CPUID.01H:ECX.[bit 21] = 1 )
x2APIC Interrupt Command register (R/W)
x2APIC Initial Count register (R/W)
x2APIC Interrupt Request register bits [31:0] (R/O)
x2APIC Interrupt Request register bits [63:32] (R/O)
x2APIC Interrupt Request register bits [95:64] (R/O)
x2APIC Interrupt Request register bits [127:96] (R/O)
x2APIC Interrupt Request register bits [159:128] (R/O)
x2APIC Interrupt Request register bits [191:160] (R/O)
x2APIC Interrupt Request register bits [223:192] (R/O)
x2APIC Interrupt Request register bits [255:224] (R/O)
x2APIC In-Service register bits [31:0] (R/O)
x2APIC In-Service register bits [63:32] (R/O)
x2APIC In-Service register bits [95:64] (R/O)
x2APIC In-Service register bits [127:96] (R/O)
x2APIC In-Service register bits [159:128] (R/O)
x2APIC In-Service register bits [191:160] (R/O)
x2APIC In-Service register bits [223:192] (R/O)
x2APIC In-Service register bits [255:224] (R/O)
x2APIC Logical Destination register (R/O)
x2APIC LVT Corrected Machine Check Interrupt register (R/W)
If ( CPUID.01H:ECX.[bit 21] = 1 )
If ( CPUID.01H:ECX.[bit 21] = 1 )
If ( CPUID.01H:ECX.[bit 21] = 1 )
x2APIC LVT Performance Monitor register (R/W)
x2APIC LVT Thermal Sensor Interrupt register (R/W)
x2APIC LVT Timer Interrupt register (R/W)
x2APIC Processor Priority register (R/O)
If ( CPUID.01H:ECX.[bit 21] = 1 )
x2APIC Spurious Interrupt Vector register (R/W)
x2APIC Trigger Mode register bits [31:0] (R/O)
x2APIC Trigger Mode register bits [63:32] (R/O)
x2APIC Trigger Mode register bits [95:64] (R/O)
x2APIC Trigger Mode register bits [127:96] (R/O)
x2APIC Trigger Mode register bits [159:128] (R/O)
x2APIC Trigger Mode register bits [191:160] (R/O)
x2APIC Trigger Mode register bits [223:192] (R/O)
x2APIC Trigger Mode register bits [255:224] (R/O)
x2APIC Task Priority register (R/W)
x2APIC Version. If ( CPUID.01H:ECX.[bit 21] = 1 )
Defined in MCA architecture but not implemented in the P6 family processors.
Defined in MCA architecture but not implemented in the P6 family processors.
Bit definitions same as MC0_STATUS.
Defined in MCA architecture but not implemented in the P6 family processors.
Bit definitions same as MC0_STATUS.
Defined in MCA architecture but not implemented in the P6 family processors.
Bit definitions same as MC0_STATUS.
Defined in MCA architecture but not implemented in P6 Family processors.
Defined in MCA architecture but not implemented in the P6 family processors.
Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Uncore B-box 0 perfmon local box control MSR.
Uncore B-box 0 perfmon local box overflow control MSR.
Uncore B-box 0 perfmon local box status MSR.
Uncore B-box 0 perfmon counter MSR.
Uncore B-box 0 perfmon counter MSR.
Uncore B-box 0 perfmon counter MSR.
Uncore B-box 0 perfmon counter MSR.
Uncore B-box 0 perfmon event select MSR.
Uncore B-box 0 perfmon event select MSR.
Uncore B-box 0 perfmon event select MSR.
Uncore B-box 0 perfmon event select MSR.
Uncore B-box 0 perfmon local box mask MSR.
Uncore B-box 0 perfmon local box match MSR.
Uncore B-box 1 perfmon local box control MSR.
Uncore B-box 1 perfmon local box overflow control MSR.
Uncore B-box 1 perfmon local box status MSR.
Uncore B-box 1 perfmon counter MSR.
Uncore B-box 1 perfmon counter MSR.
Uncore B-box 1 perfmon counter MSR.
Uncore B-box 1 perfmon counter MSR.
Uncore B-box 1 perfmon event select MSR.
Uncore B-box 1 perfmon event select MSR.
Uncore B-box 1 perfmon event select MSR.
Uncore B-box 1vperfmon event select MSR.
Uncore B-box 1 perfmon local box mask MSR.
Uncore B-box 1 perfmon local box match MSR.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Uncore C-box 0 perfmon local box control MSR.
Uncore C-box 0 perfmon local box overflow control MSR.
Uncore C-box 0 perfmon local box status MSR.
Uncore C-box 0 perfmon counter MSR.
Uncore C-box 0 perfmon counter MSR.
Uncore C-box 0 perfmon counter MSR.
Uncore C-box 0 perfmon counter MSR.
Uncore C-box 0 perfmon counter MSR.
Uncore C-box 0 perfmon counter MSR.
Uncore C-box 0 perfmon event select MSR.
Uncore C-box 0 perfmon event select MSR.
Uncore C-box 0 perfmon event select MSR.
Uncore C-box 0 perfmon event select MSR.
Uncore C-box 0 perfmon event select MSR.
Uncore C-box 0 perfmon event select MSR.
Uncore C-box 1 perfmon local box control MSR.
Uncore C-box 1 perfmon local box overflow control MSR.
Uncore C-box 1 perfmon local box status MSR.
Uncore C-box 1 perfmon counter MSR.
Uncore C-box 1 perfmon counter MSR.
Uncore C-box 1 perfmon counter MSR.
Uncore C-box 1 perfmon counter MSR.
Uncore C-box 1 perfmon counter MSR.
Uncore C-box 1 perfmon counter MSR.
Uncore C-box 1 perfmon event select MSR.
Uncore C-box 1 perfmon event select MSR.
Uncore C-box 1 perfmon event select MSR.
Uncore C-box 1 perfmon event select MSR.
Uncore C-box 1 perfmon event select MSR.
Uncore C-box 1 perfmon event select MSR.
Uncore C-box 2 perfmon local box control MSR.
Uncore C-box 2 perfmon local box overflow control MSR.
Uncore C-box 2 perfmon local box status MSR.
Uncore C-box 2 perfmon counter MSR.
Uncore C-box 2 perfmon counter MSR.
Uncore C-box 2 perfmon counter MSR.
Uncore C-box 2 perfmon counter MSR.
Uncore C-box 2 perfmon counter MSR.
Uncore C-box 2 perfmon counter MSR.
Uncore C-box 2 perfmon event select MSR.
Uncore C-box 2 perfmon event select MSR.
Uncore C-box 2 perfmon event select MSR.
Uncore C-box 2 perfmon event select MSR.
Uncore C-box 2 perfmon event select MSR.
Uncore C-box 2 perfmon event select MSR.
Uncore C-box 3 perfmon local box control MSR.
Uncore C-box 3 perfmon local box overflow control MSR.
Uncore C-box 3 perfmon local box status MSR.
Uncore C-box 3 perfmon counter MSR.
Uncore C-box 3 perfmon counter MSR.
Uncore C-box 3 perfmon counter MSR.
Uncore C-box 3 perfmon counter MSR.
Uncore C-box 3 perfmon counter MSR.
Uncore C-box 3 perfmon counter MSR.
Uncore C-box 3 perfmon event select MSR.
Uncore C-box 3 perfmon event select MSR.
Uncore C-box 3 perfmon event select MSR.
Uncore C-box 3 perfmon event select MSR.
Uncore C-box 3 perfmon event select MSR.
Uncore C-box 3 perfmon event select MSR.
Uncore C-box 4 perfmon local box control MSR.
Uncore C-box 4 perfmon local box overflow control MSR.
Uncore C-box 4 perfmon local box status MSR.
Uncore C-box 4 perfmon counter MSR.
Uncore C-box 4 perfmon counter MSR.
Uncore C-box 4 perfmon counter MSR.
Uncore C-box 4 perfmon counter MSR.
Uncore C-box 4 perfmon counter MSR.
Uncore C-box 4 perfmon counter MSR.
Uncore C-box 4 perfmon event select MSR.
Uncore C-box 4 perfmon event select MSR.
Uncore C-box 4 perfmon event select MSR.
Uncore C-box 4 perfmon event select MSR.
Uncore C-box 4 perfmon event select MSR.
Uncore C-box 4 perfmon event select MSR.
Uncore C-box 5 perfmon local box control MSR.
Uncore C-box 5 perfmon local box overflow control MSR.
Uncore C-box 5 perfmon local box status MSR.
Uncore C-box 5 perfmon counter MSR.
Uncore C-box 5 perfmon counter MSR.
Uncore C-box 5 perfmon counter MSR.
Uncore C-box 5 perfmon counter MSR.
Uncore C-box 5 perfmon counter MSR.
Uncore C-box 5 perfmon counter MSR.
Uncore C-box 5 perfmon event select MSR.
Uncore C-box 5 perfmon event select MSR.
Uncore C-box 5 perfmon event select MSR.
Uncore C-box 5 perfmon event select MSR.
Uncore C-box 5 perfmon event select MSR.
Uncore C-box 5 perfmon event select MSR.
Uncore C-box 6 perfmon local box control MSR.
Uncore C-box 6 perfmon local box overflow control MSR.
Uncore C-box 6 perfmon local box status MSR.
Uncore C-box 6 perfmon counter MSR.
Uncore C-box 6 perfmon counter MSR.
Uncore C-box 6 perfmon counter MSR.
Uncore C-box 6 perfmon counter MSR.
Uncore C-box 6 perfmon counter MSR.
Uncore C-box 6 perfmon counter MSR.
Uncore C-box 6 perfmon event select MSR.
Uncore C-box 6 perfmon event select MSR.
Uncore C-box 6 perfmon event select MSR.
Uncore C-box 6 perfmon event select MSR.
Uncore C-box 6 perfmon event select MSR.
Uncore C-box 6 perfmon event select MSR.
Uncore C-box 7 perfmon local box control MSR.
Uncore C-box 7 perfmon local box overflow control MSR.
Uncore C-box 7 perfmon local box status MSR.
Uncore C-box 7 perfmon counter MSR.
Uncore C-box 7 perfmon counter MSR.
Uncore C-box 7 perfmon counter MSR.
Uncore C-box 7 perfmon counter MSR.
Uncore C-box 7 perfmon counter MSR.
Uncore C-box 7 perfmon counter MSR.
Uncore C-box 7 perfmon event select MSR.
Uncore C-box 7 perfmon event select MSR.
Uncore C-box 7 perfmon event select MSR.
Uncore C-box 7 perfmon event select MSR.
Uncore C-box 7 perfmon event select MSR.
Uncore C-box 7 perfmon event select MSR.
Uncore C-box 8 perfmon local box control MSR.
Uncore C-box 8 perfmon local box overflow control MSR.
Uncore C-box 8 perfmon local box status MSR.
Uncore C-box 8 perfmon counter MSR.
Uncore C-box 8 perfmon counter MSR.
Uncore C-box 8 perfmon counter MSR.
Uncore C-box 8 perfmon counter MSR.
Uncore C-box 8 perfmon counter MSR.
Uncore C-box 8 perfmon counter MSR.
Uncore C-box 8 perfmon event select MSR.
Uncore C-box 8 perfmon event select MSR.
Uncore C-box 8 perfmon event select MSR.
Uncore C-box 8 perfmon event select MSR.
Uncore C-box 8 perfmon event select MSR.
Uncore C-box 8 perfmon event select MSR.
Uncore C-box 9 perfmon local box control MSR.
Uncore C-box 9 perfmon local box overflow control MSR.
Uncore C-box 9 perfmon local box status MSR.
Uncore C-box 9 perfmon counter MSR.
Uncore C-box 9 perfmon counter MSR.
Uncore C-box 9 perfmon counter MSR.
Uncore C-box 9 perfmon counter MSR.
Uncore C-box 9 perfmon counter MSR.
Uncore C-box 9 perfmon counter MSR.
Uncore C-box 9 perfmon event select MSR.
Uncore C-box 9 perfmon event select MSR.
Uncore C-box 9 perfmon event select MSR.
Uncore C-box 9 perfmon event select MSR.
Uncore C-box 9 perfmon event select MSR.
Uncore C-box 9 perfmon event select MSR.
ConfigTDP Control (R/W)
ConfigTDP Level 1 ratio and power level (R/O)
ConfigTDP Level 2 ratio and power level (R/O)
Nominal TDP Ratio (R/O)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.9.1, MSR_DEBUGCTLA MSR.
Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors).
DRAM Energy Status (R/O) See Section 14.7.5, DRAM RAPL Domain.
DRAM Performance Throttling Status (R/O) See Section 14.7.5, DRAM RAPL Domain.
DRAM RAPL Parameters (R/W) See Section 14.7.5, DRAM RAPL Domain.
DRAM RAPL Power Limit Control (R/W) See Section 14.7.5, DRAM RAPL Domain.
Processor Frequency Configuration The bit field layout of this MSR varies according to the MODEL value in the CPUID version information. The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or greater than 2. (R) The field Indicates the current processor frequency configuration.
Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
Processor Soft Power-On Configuration (R/W) Enables and disables processor features.
Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
EFSB DRDY Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.
EFSB DRDY Event Control and Counter Register (R/W)
GBUSQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.
GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2
GSNPQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.
GSNPQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2
FSB Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.
FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2
FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2
FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2
L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2
MC Bank Error Configuration (R/W)
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Intel Atom microarchitecture:
Trace End Address 0
Trace Start Address 0
Trace End Address 1
Trace Start Address 1
Trace End Address 3
Trace Start Address 3
Trace End Address 4
Trace Start Address 4
Trace Filter CR3 Match Register (R/W)
Trace Control Register (R/W)
Trace Output Base Register (R/W)
Trace Output Mask Pointers Register (R/W)
Tracing Status Register (R/W)
TSX Ctrl Register for TSX Async Abot (TAA) Migration. See Volume 3A, Section 2.1, Table 2-2.
IFSB BUSQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.
IFSB BUSQ Event Control and Counter Register (R/W)
IFSB Latency Event Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.
IFSB Latency Event Control Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.
IFSB SNPQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.
IFSB SNPQ Event Control and Counter Register (R/W)
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.
See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Last Branch Record 0 (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H- 68FH and 6C0H-6CFH.
Last Branch Record 0 From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction for one of the last eight branches, exceptions, or interrupts taken by the processor. See also: Last Branch Record Stack TOS at 1C9H Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors).
Last Branch Record 0 (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.9, Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture).
Last Branch Record 1 (R/W) See description of MSR_LASTBRANCH_0.
Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 2 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 3 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 4 (R/W) See description of MSR_LASTBRANCH_0.
Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 5 (R/W) See description of MSR_LASTBRANCH_0.
Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 6 (R/W) See description of MSR_LASTBRANCH_0.
Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 7 (R/W) See description of MSR_LASTBRANCH_0.
Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 8 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 8 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 9 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 9 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 10 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 10 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 11 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 11 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 12 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 12 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 13 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 13 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 14 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 14 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record 15 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
Last Branch Record 15 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
Last Branch Record Stack TOS (R/W) Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that points the index of the MSR containing the most recent branch record). See Section 17.9.2, LBR Stack for Processors Based on Intel NetBurst® Microarchitecture ; and addresses 1DBH-1DEH and 680H-68FH.
Last Branch Record Filtering Select Register (R/W) See Section 17.6.2, Filtering of Last Branch Records.
Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors) and Section 17.12.2, Last Branch and Last Exception MSRs.
Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors) and Section 17.12.2, Last Branch and Last Exception MSRs.
Uncore M-box 0 perfmon local box address mask MSR.
Uncore M-box 0 perfmon local box address match MSR.
Uncore M-box 0 perfmon local box control MSR.
Uncore M-box 0 perfmon local box overflow control MSR.
Uncore M-box 0 perfmon local box status MSR.
Uncore M-box 0 perfmon counter MSR.
Uncore M-box 0 perfmon counter MSR.
Uncore M-box 0 perfmon counter MSR.
Uncore M-box 0 perfmon counter MSR.
Uncore M-box 0 perfmon counter MSR.
Uncore M-box 0 perfmon counter MSR.
Uncore M-box 0 perfmon DSP unit select MSR.
Uncore M-box 0 perfmon event select MSR.
Uncore M-box 0 perfmon event select MSR.
Uncore M-box 0 perfmon event select MSR.
Uncore M-box 0 perfmon event select MSR.
Uncore M-box 0 perfmon event select MSR.
Uncore M-box 0 perfmon event select MSR.
Uncore M-box 0 perfmon ISS unit select MSR.
Uncore M-box 0 perfmon MAP unit select MSR.
Uncore M-box 0 perfmon local box address match/mask config MSR.
Uncore M-box 0 perfmon MIC THR select MSR.
Uncore M-box 0 perfmon PGT unit select MSR.
Uncore M-box 0 perfmon PLD unit select MSR.
Uncore M-box 0 perfmon time stamp unit select MSR.
Uncore M-box 0 perfmon ZDP unit select MSR.
Uncore M-box 1 perfmon local box address mask MSR.
Uncore M-box 1 perfmon local box address match MSR.
Uncore M-box 1 perfmon local box control MSR.
Uncore M-box 1 perfmon local box overflow control MSR.
Uncore M-box 1 perfmon local box status MSR.
Uncore M-box 1 perfmon counter MSR.
Uncore M-box 1 perfmon counter MSR.
Uncore M-box 1 perfmon counter MSR.
Uncore M-box 1 perfmon counter MSR.
Uncore M-box 1 perfmon counter MSR.
Uncore M-box 1 perfmon counter MSR.
Uncore M-box 1 perfmon DSP unit select MSR.
Uncore M-box 1 perfmon event select MSR.
Uncore M-box 1 perfmon event select MSR.
Uncore M-box 1 perfmon event select MSR.
Uncore M-box 1 perfmon event select MSR.
Uncore M-box 1 perfmon event select MSR.
Uncore M-box 1 perfmon event select MSR.
Uncore M-box 1 perfmon ISS unit select MSR.
Uncore M-box 1 perfmon MAP unit select MSR.
Uncore M-box 1 perfmon local box address match/mask config MSR.
Uncore M-box 1 perfmon MIC THR select MSR.
Uncore M-box 1 perfmon PGT unit select MSR.
Uncore M-box 1 perfmon PLD unit select MSR.
Uncore M-box 1 perfmon time stamp unit select MSR.
Uncore M-box 1 perfmon ZDP unit select MSR.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
Always 0 (CMCI not supported).
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 15.3.2.2, IA32_MCi_STATUS MSRS. and Chapter 23.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
See Section 15.3.2.3, IA32_MCi_ADDR MSRs.
See Section 15.3.2.1, IA32_MCi_CTL MSRs.
See Section 15.3.2.4, IA32_MCi_MISC MSRs.
See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.
Machine Check Miscellaneous See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R8 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R9D/R9 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R10 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R11 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R12 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R13 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check R14 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EAX/RAX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EBP/RBP Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EBX/RBX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check ECX/RCX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EDI/RDI Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EDX/RDX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EFLAGS/RFLAG Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check EIP/RIP Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
Machine Check ESI/RSI Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
See http://biosbits.org.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.3, CCCR MSRs.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.2, Performance Counters.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Offcore Response Event Select Register (R/W)
Offcore Response Event Select Register (R/W)
Precise Event-Based Sampling (PEBS) (R/W) Controls the enabling of precise event sampling and replay tagging.
see See Section 18.7.1.2, Load Latency Performance Monitoring Facility.
See Table 19-26.
RO. This applies to processors that do not support architectural perfmon version 2.
Fixed-Function Performance Counter Register 0 (R/W)
Fixed-Function Performance Counter Register 1 (R/W)
Fixed-Function Performance Counter Register 2 (R/W)
Fixed-Function-Counter Control Register (R/W)
See Section 18.4.2, Global Counter Control Facilities.
See Section 18.4.2, Global Counter Control Facilities.
See Section 18.4.2, Global Counter Control Facilities.
Package C3 Interrupt Response Limit (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Package C6 Interrupt Response Limit (R/W) This MSR defines the budget allocated for the package to exit from C6 to a C0 state, where interrupt request can be delivered to the core and serviced. Additional core-exit latency amy be applicable depending on the actual C-state the core is in. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Package C7 Interrupt Response Limit (R/W) This MSR defines the budget allocated for the package to exit from C7 to a C0 state, where interrupt request can be delivered to the core and serviced. Additional core-exit latency amy be applicable depending on the actual C-state the core is in. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.
Package C2 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Package C6 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.
C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States. See http://biosbits.org.
PKG Energy Status (R/O) See Section 14.7.3, Package RAPL Domain.
Package RAPL Perf Status (R/O)
PKG RAPL Parameters (R/W) See Section 14.7.3, Package RAPL Domain.
PKG RAPL Power Limit Control (R/W) See Section 14.7.3, Package RAPL Domain.
Platform Feature Requirements (R)
Model Specific Platform ID (R)
see http://biosbits.org.
Power Management IO Redirection in C-state (R/W) See http://biosbits.org.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Power Control Register. See http://biosbits.org.
PP0 Energy Status (R/O) See Section 14.7.4, PP0/PP1 RAPL Domains.
PP0 Performance Throttling Status (R/O) See Section 14.7.4, PP0/PP1 RAPL Domains.
PP0 Balance Policy (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.
PP0 RAPL Power Limit Control (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.
PP1 Energy Status (R/O) See Section 14.7.4, PP0/PP1 RAPL Domains.
PP1 Balance Policy (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.
PP1 RAPL Power Limit Control (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.
Uncore R-box 0 perfmon local box control MSR.
Uncore R-box 0 perfmon local box overflow control MSR.
Uncore R-box 0 perfmon local box status MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon counter MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon event select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
Uncore R-box 1 perfmon local box control MSR.
Uncore R-box 1 perfmon local box overflow control MSR.
Uncore R-box 1 perfmon local box status MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1perfmon counter MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1 perfmon counter MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon event select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.7.1, RAPL Interfaces.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Uncore S-box 0 perfmon local box control MSR.
Uncore S-box 0 perfmon local box overflow control MSR.
Uncore S-box 0 perfmon local box status MSR.
Uncore S-box 0 perfmon counter MSR.
Uncore S-box 0 perfmon counter MSR.
Uncore S-box 0 perfmon counter MSR.
Uncore S-box 0 perfmon counter MSR.
Uncore S-box 0 perfmon event select MSR.
Uncore S-box 0 perfmon event select MSR.
Uncore S-box 0 perfmon event select MSR.
Uncore S-box 0 perfmon event select MSR.
Uncore S-box 0 perfmon local box mask MSR.
Uncore S-box 0 perfmon local box match MSR.
Uncore S-box 1 perfmon local box control MSR.
Uncore S-box 1 perfmon local box overflow control MSR.
Uncore S-box 1 perfmon local box status MSR.
Uncore S-box 1 perfmon counter MSR.
Uncore S-box 1 perfmon counter MSR.
Uncore S-box 1 perfmon counter MSR.
Uncore S-box 1 perfmon counter MSR.
Uncore S-box 1 perfmon event select MSR.
Uncore S-box 1 perfmon event select MSR.
Uncore S-box 1 perfmon event select MSR.
Uncore S-box 1 perfmon event select MSR.
Uncore S-box 1 perfmon local box mask MSR.
Uncore S-box 1 perfmon local box match MSR.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
SMI Counter (R/O)
SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package . Available only while in SMM.
SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package . Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM.
Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.
System Management Mode Physical Address Mask register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM..
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
Thermal Monitor 2 Control.
ConfigTDP Control (R/W)
See http://biosbits.org.
Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1
See Section 18.12.1, ESCR MSRs.
See Section 18.12.1, ESCR MSRs.
See Section 18.7.2.3, Uncore Address/Opcode Match MSR.
See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
Uncore Arb unit, counter 0 event select MSR
Uncore Arb unit, counter 1 event select MSR
Uncore Arb unit, performance counter 0
Uncore Arb unit, performance counter 1
Uncore C-Box 0, counter 0 event select MSR
Uncore C-Box 0, counter 1 event select MSR
Uncore C-Box 0, performance counter 0
Uncore C-Box 0, performance counter 1
Uncore C-Box 1, counter 0 event select MSR
Uncore C-Box 1, counter 1 event select MSR
Uncore C-Box 1, performance counter 0
Uncore C-Box 1, performance counter 1
Uncore C-Box 2, counter 0 event select MSR
Uncore C-Box 2, counter 1 event select MSR
Uncore C-Box 2, performance counter 0
Uncore C-Box 2, performance counter 1
Uncore C-Box 3, counter 0 event select MSR
Uncore C-Box 3, counter 1 event select MSR.
Uncore C-Box 3, performance counter 0.
Uncore C-Box 3, performance counter 1.
Uncore C-Box configuration information (R/O)
Uncore fixed counter
Uncore fixed counter control (R/W)
Uncore PMU global control
Uncore PMU main status
Uncore U-box perfmon counter MSR.
Uncore U-box perfmon event select MSR.
Uncore U-box perfmon global control MSR.
Uncore U-box perfmon global overflow control MSR.
Uncore U-box perfmon global status MSR.
Uncore W-box perfmon local box control MSR.
Uncore W-box perfmon local box overflow control MSR.
Uncore W-box perfmon local box status MSR.
Uncore W-box perfmon counter MSR.
Uncore W-box perfmon counter MSR.
Uncore W-box perfmon counter MSR.
Uncore W-box perfmon counter MSR.
Uncore W-box perfmon event select MSR.
Uncore W-box perfmon event select MSR.
Uncore W-box perfmon event select MSR.
Uncore W-box perfmon event select MSR.
Uncore W-box perfmon fixed counter
Uncore U-box perfmon fixed counter control MSR
See Section 35.16, MSRs in Pentium Processors, and see Table 35-2.
See Section 35.16, MSRs in Pentium Processors, and see Table 35-2.
CS register target for CPL 0 code
CPL 0 code entry point
Stack pointer for CPL 0 stack
Test Control Register
See Section 17.13, Time-Stamp Counter.