Expand description
Information about the xAPIC for the local APIC.
Table 10-1 Local APIC Register Address Map the MMIO base values are found in this file.
Structs
State for the XAPIC driver.
Constants
EOI register. Write-only.
Error Status Register (ESR). Read/write. See Section 10.5.3.
Interrupt Command Register (ICR). Read/write. See Figure 10-28 for reserved bits
Interrupt Command Register (ICR). Read/write. See Figure 10-28 for reserved bits
Local APIC ID register. Read-only. See Section 10.12.5.1 for initial values.
Interrupt Request Register (IRR); bits 31:0. Read-only.
IRR bits 63:32. Read-only.
IRR bits 95:64. Read-only.
IRR bits 127:96. Read-only.
IRR bits 159:128. Read-only.
IRR bits 191:160. Read-only.
IRR bits 223:192. Read-only.
IRR bits 255:224. Read-only.
In-Service Register (ISR); bits 31:0. Read-only.
ISR bits 63:32. Read-only.
ISR bits 95:64. Read-only.
ISR bits 127:96. Read-only.
ISR bits 159:128. Read-only.
ISR bits 191:160. Read-only.
ISR bits 223:192. Read-only.
ISR bits 255:224. Read-only.
Logical Destination Register (LDR). Read/write in xAPIC mode.
LVT CMCI register. Read/write. See Figure 10-8 for reserved bits.
LVT Error register. Read/write. See Figure 10-8 for reserved bits.
LVT LINT0 register. Read/write. See Figure 10-8 for reserved bits.
LVT LINT1 register. Read/write. See Figure 10-8 for reserved bits.
LVT Performance Monitoring register. Read/write. See Figure 10-8 for reserved bits.
LVT Thermal Sensor register. Read/write. See Figure 10-8 for reserved bits.
LVT Timer register. Read/write. See Figure 10-8 for reserved bits.
Processor Priority Register (PPR). Read-only.
Spurious Interrupt Vector Register (SVR). Read/write. See Section 10.9 for reserved bits.
Current Count register (for Timer). Read-only.
Divide Configuration Register (DCR; for Timer). Read/write. See Figure 10-10 for reserved bits.
Initial Count register (for Timer). Read/write.
Trigger Mode Register (TMR); bits 31:0. Read-only.
TMR bits 63:32. Read-only.
TMR bits 95:64. Read-only.
TMR bits 127:96. Read-only.
TMR bits 159:128. Read-only.
TMR bits 191:160. Read-only.
TMR bits 223:192. Read-only.
TMR bits 255:224. Read-only.
Task Priority Register (TPR). Read/write. Bits 31:8 are reserved.
Local APIC Version register. Read-only. Same version used in xAPIC mode and x2APIC mode.