Module x86::xapic

Information about the xAPIC and x2APIC mode for the local APIC.

Table 10-1 Local APIC Register Address Map the MMIO base values are found in this file, for x2APIC MSR see msr.rs.

Constants

XAPIC_EOI	EOI register. Write-only.
XAPIC_ESR	Error Status Register (ESR). Read/write. See Section 10.5.3.
XAPIC_ICR0	Interrupt Command Register (ICR). Read/write. See Figure 10-28 for reserved bits
XAPIC_ICR1	Interrupt Command Register (ICR). Read/write. See Figure 10-28 for reserved bits
XAPIC_ID	Local APIC ID register. Read-only. See Section 10.12.5.1 for initial values.
XAPIC_IRR0	Interrupt Request Register (IRR); bits 31:0. Read-only.
XAPIC_IRR1	IRR bits 63:32. Read-only.
XAPIC_IRR2	IRR bits 95:64. Read-only.
XAPIC_IRR3	IRR bits 127:96. Read-only.
XAPIC_IRR4	IRR bits 159:128. Read-only.
XAPIC_IRR5	IRR bits 191:160. Read-only.
XAPIC_IRR6	IRR bits 223:192. Read-only.
XAPIC_IRR7	IRR bits 255:224. Read-only.
XAPIC_ISR0	In-Service Register (ISR); bits 31:0. Read-only.
XAPIC_ISR1	ISR bits 63:32. Read-only.
XAPIC_ISR2	ISR bits 95:64. Read-only.
XAPIC_ISR3	ISR bits 127:96. Read-only.
XAPIC_ISR4	ISR bits 159:128. Read-only.
XAPIC_ISR5	ISR bits 191:160. Read-only.
XAPIC_ISR6	ISR bits 223:192. Read-only.
XAPIC_ISR7	ISR bits 255:224. Read-only.
XAPIC_LDR	Logical Destination Register (LDR). Read/write in xAPIC mode.
XAPIC_LVT_CMCI	LVT CMCI register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_LVT_ERROR	LVT Error register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_LVT_LINT0	LVT LINT0 register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_LVT_LINT1	LVT LINT1 register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_LVT_PMI	LVT Performance Monitoring register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_LVT_THERMAL	LVT Thermal Sensor register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_LVT_TIMER	LVT Timer register. Read/write. See Figure 10-8 for reserved bits.
XAPIC_PPR	Processor Priority Register (PPR). Read-only.
XAPIC_SVR	Spurious Interrupt Vector Register (SVR). Read/write. See Section 10.9 for reserved bits.
XAPIC_TIMER_CURRENT_COUNT	Current Count register (for Timer). Read-only.
XAPIC_TIMER_DIV_CONF	Divide Configuration Register (DCR; for Timer). Read/write. See Figure 10-10 for reserved bits.
XAPIC_TIMER_INIT_COUNT	Initial Count register (for Timer). Read/write.
XAPIC_TMR0	Trigger Mode Register (TMR); bits 31:0. Read-only.
XAPIC_TMR1	TMR bits 63:32. Read-only.
XAPIC_TMR2	TMR bits 95:64. Read-only.
XAPIC_TMR3	TMR bits 127:96. Read-only.
XAPIC_TMR4	TMR bits 159:128. Read-only.
XAPIC_TMR5	TMR bits 191:160. Read-only.
XAPIC_TMR6	TMR bits 223:192. Read-only.
XAPIC_TMR7	TMR bits 255:224. Read-only.
XAPIC_TPR	Task Priority Register (TPR). Read/write. Bits 31:8 are reserved.
XAPIC_VERSION	Local APIC Version register. Read-only. Same version used in xAPIC mode and x2APIC mode.