Crate x86_pic 

Support for the 8259 Programmable Interrupt Controller, which handles basic I/O interrupts.
In multicore mode, we would apparently need to replace this with an APIC interface.

A single PIC handles up to eight vectored priority interrupts for the CPU. By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines, however we only have two chained instances that can handle 16 lines. Can be programmed either in edge triggered, or in level triggered mode. PIC uses CHANNEL0 from the PIT (Programmable Interval Timer), the frequency of which can be adjusted based on it’s configuration. Individual bits of IRQ register within the PIC can be masked out by the software.

Typical Application.

// Somewhere alongside other statics...
use x86-pic::ChainedPics;
use spin::Mutex;
pub static PROGRAMMABLE_INTERRUPT_CONTROLLER: Mutex<Option<ChainedPics>> = Mutex::new(None);

Fully nested

...
// Somewhere in the OS initialization...
 
/* Memory init code, IDT and stuff... */

let mut pic = ChainedPics::new_contiguous(32); // i.e IRQ0 => interrupt vector 32.
pic.initialize();

PROGRAMMABLE_INTERRUPT_CONTROLLER.lock().replace(pic);
/* Here we can enable interrupts freely :) */

...
// Somewhere in interrupt handling module. 
 
#[no_mangle]
unsafe extern "x86-interrupt" fn timer_interrupt_handler(mut stack_frame: InterruptStackFrame) {

    /*
     * Some interrupt handling logic and stuff.
     *  */
     
    // Sending the EOI.
    PROGRAMMABLE_INTERRUPT_CONTROLLER.lock().as_mut().map(|pic| {
        pic.notify_end_of_interrupt(32)
    });
}
...

#[no_mangle]
unsafe extern "x86-interrupt" fn parallel_port1_handler(mut stack_frame: InterruptStackFrame) {
    let mut pic = PROGRAMMABLE_INTERRUPT_CONTROLLER.lock();
 
    // Checking if the interrupt was legit. (please look `x86_pic::ChainedPics::is_spurious`)
    if pic.as_mut().map(|pic| !pic.is_spurious(39)).unwrap_or(false) {
 
        /*  
         * Some interrupt handling logic and stuff.
         *  */
        println!("The interrupt was legit!");
 
        // Sending the EOI.
        pic.as_mut().map(|pic| {
            pic.notify_end_of_interrupt(39)
        });
    } else {
        println!("A spurious interrupt! Do not handle that!");
    }
}

Structs

ChainedPics

A x86 setup of Chained PICs.

IRR

Read the Interrupt Request Register (IRR).

ISR

Read the Interrupt Service Register (ISR).

IrqMask

IRQ Flags for 16 PIC Interrupts.

Enums

PicOperationMode

Operation Mode for PIC Controller.