[][src]Module vhdl_parser::ast

Modules

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Structs

AliasDeclaration

LRM 6.6 Alias declarations

Alternative
ArchitectureBody

LRM 3.3 Architecture bodies

AssertStatement

LRM 10.3 Assertion statement

AssociationElement

LRM 6.5.7 Association Lists

AttributeDeclaration

LRM 6.7 Attribute declarations

AttributeName

LRM 8.6 Attribute names

AttributeSpecification

LRM 7.2 Attribute specification

BindingIndication

LRM 7.3.2 Binding indication

BitString

LRM 15.8 Bit string literals

BlockConfiguration

LRM 3.4 Configuration declarations

BlockStatement

LRM 11.2 Block statement

ComponentConfiguration

LRM 3.4 Configuration declarations

ComponentDeclaration

LRM 6.8 Component declarations

ComponentSpecification

LRM 7.3 Configuration specification

ConcurrentAssertStatement

LRM 11.5 Concurrent assertion statements

ConcurrentProcedureCall

LRM 11.4 Concurrent procedure call statements

ConcurrentSignalAssignment

11.6 Concurrent signal assignment statements

Conditional
Conditionals
ConfigurationDeclaration

LRM 3.4 Configuration declarations

ConfigurationSpecification

LRM 7.3 Configuration specification

ContextDeclaration

LRM 13.4 Context clauses

ContextReference

LRM 13.4 Context clauses

DesignFile
ElementConstraint

LRM: record_element_constraint

ElementDeclaration

LRM 5.3.3 Record types

EntityDeclaration

LRM 3.2 Entity declarations

EntityTag

LRM 7.2 Attribute specification

ExitStatement

LRM 10.12 Exit statement

ExternalName

LRM 8.7 External names

FileDeclaration
ForGenerateStatement

11.8 Generate statements

FunctionCall

LRM 9.3.4 Function calls

FunctionSpecification

LRM 4.2 Subprogram declaration

GenerateBody

11.8 Generate statements

InstantiationStatement

11.7 Component instantiation statements

InterfaceFileDeclaration
InterfaceObjectDeclaration

LRM 6.5.2 Interface object declarations

InterfacePackageDeclaration

LRM 6.5.5 Interface package declaration

LabeledConcurrentStatement

LRM 11. Concurrent statements

LabeledSequentialStatement

LRM 10. Sequential statements

LibraryClause

LRM 13. Design units and their analysis

LoopStatement

LRM 10.10 Loop statement

NextStatement

LRM 10.11 Next statement

ObjectDeclaration
PackageBody

LRM 4.8 Package bodies

PackageDeclaration

LRM 4.7 Package declarations

PackageInstantiation

LRM 4.9 Package instatiation declaration

PhysicalTypeDeclaration

LRM 5.4.2 Physical type declaration

PortClause
ProcedureSpecification

LRM 4.2 Subprogram declaration

ProcessStatement

LRM 11.3 Process statement

ProtectedTypeBody

LRM 5.6.3 Protected type bodies

ProtectedTypeDeclaration

LRM 5.6.2 Protected type declarations

QualifiedExpression

LRM 9.3.5 Qualified expressions

RangeConstraint
RecordElementResolution

LRM 6.3 Subtype declarations

ReportStatement

LRM 10.4 Report statement

ReturnStatement

LRM 10.13 Return statement

Selection
SignalAssignment

LRM 10.5 Signal assignment statement

SignalForceAssignment
SignalReleaseAssignment
SubprogramBody

LRM 4.3 Subprogram bodies

SubtypeIndication

LRM 6.3 Subtype declarations

TypeDeclaration

LRM 6.2 Type declarations

UnitId
UseClause

LRM 12.4. Use clauses

VUnitBindingIndication

LRM 7.3.4 Verification unit binding indication

VariableAssignment

LRM 10.6 Variable assignment statement

WaitStatement

LRM 10.2 Wait statement

WaveformElement

LRM 10.5 Signal assignment statement

WithRef

An item which has a reference to a declaration

Enums

AbstractLiteral

LRM 15.5 Abstract literals

ActualPart

LRM 6.5.7 Association Lists

Allocator

LRM 9.3.7 Allocators

AnyDesignUnit

LRM 13.1 Design units

AnyKind
AnyPrimaryUnit

LRM 13.1 Design units

AnySecondaryUnit

LRM 13.1 Design units

ArrayIndex

LRM 5.3 Array Types

AssignmentRightHand

LRM 10.5 Signal assignment statement LRM 10.6 Variable assignment statement

Attribute

LRM 7.2 Attribute specification

BaseSpecifier

LRM 15.8 Bit string literals

Binary
Choice

LRM 9.3.3 Aggregates

ConcurrentStatement

LRM 11. Concurrent statements

ConfigurationDeclarativeItem

LRM 3.4 Configuration declarations

ConfigurationItem

LRM 3.4 Configuration declarations

ContextItem

LRM 13.4 Context clauses

Declaration
DelayMechanism

LRM 10.5 Signal assignment statement

Designator
Direction
DiscreteRange

LRM discrete_range discrete_range ::= discrete_subtype_indication | range range ::= range_attribute_name | simple_expression direction simple_expression

ElementAssociation

LRM 9.3.3 Aggregates

EntityAspect

LRM 7.3.2 Binding indication

EntityClass

LRM 7.2 Attribute specification

EntityName

LRM 7.2 Attribute specification

EnumerationLiteral

LRM 5.2.2 Enumeration types

Expression

LRM 9. Expressions

ExternalObjectClass

LRM 8.7 External names

ExternalPath

LRM 8.7 External names

ForceMode
InstantiatedUnit

11.7 Component instantiation statements

InstantiationList

LRM 7.3 Configuration specification

InterfaceDeclaration
InterfacePackageGenericMapAspect

LRM 6.5.5 Interface package declaration

IterationScheme

LRM 10.10 Loop statement

Literal

LRM 9.3.2 Literals

Mode
Name

LRM 8. Names

ObjectClass

LRM 6.4.2 Object Declarations

PrimaryKind
ProtectedTypeDeclarativeItem

LRM 5.6.2 Protected type declarations

Range
ResolutionIndication

LRM 6.3 Subtype declarations

SecondaryKind
SelectedName

LRM 8. Names A subset of a full name allowing only selected name

SensitivityList
SequentialStatement

LRM 10. Sequential statements

Signature

LRM 4.5.3 Signatures

SubprogramDeclaration
SubprogramDefault
SubprogramDesignator
SubtypeConstraint
Target

LRM 10.5 Signal assignment statement

TypeDefinition

LRM 5 Types

Unary
UnitKey

Without Kind to get name conflict between different primary units

Waveform

LRM 10.5 Signal assignment statement

Traits

HasDesignator
HasIdent
HasPrimaryIdent

Primary identifier in secondary units

HasUnitId

Functions

capitalize

Upper case first letter

to_simple_name

Type Definitions

CaseGenerateStatement
CaseStatement

LRM 10.9 Case statement

ConditionalExpression
ConditionalExpressions
ContextClause
Ident
IfGenerateStatement

11.8 Generate statements

IfStatement

LRM 10.8 If statement