valheim_asm/isa/
rv64.rs

1use crate::isa::typed::{AQ, Imm32, Rd, RL, RoundingMode, Rs1, Rs2, Shamt};
2
3/// typed RV64 instructions
4#[derive(Copy, Clone, Debug, Eq, PartialEq)]
5#[allow(non_camel_case_types)]
6pub enum RV64Instr {
7  // RV64I
8  LWU(Rd, Rs1, Imm32<11, 0>),
9  LD(Rd, Rs1, Imm32<11, 0>),
10  SD(Rs1, Rs2, Imm32<11, 0>),
11  SLLI(Rd, Rs1, Shamt),
12  SRLI(Rd, Rs1, Shamt),
13  SRAI(Rd, Rs1, Shamt),
14  ADDIW(Rd, Rs1, Imm32<11, 0>),
15  SLLIW(Rd, Rs1, Shamt),
16  SRLIW(Rd, Rs1, Shamt),
17  SRAIW(Rd, Rs1, Shamt),
18  ADDW(Rd, Rs1, Rs2),
19  SUBW(Rd, Rs1, Rs2),
20  SLLW(Rd, Rs1, Rs2),
21  SRLW(Rd, Rs1, Rs2),
22  SRAW(Rd, Rs1, Rs2),
23
24  // RV64M
25  MULW(Rd, Rs1, Rs2),
26  DIVW(Rd, Rs1, Rs2),
27  DIVUW(Rd, Rs1, Rs2),
28  REMW(Rd, Rs1, Rs2),
29  REMUW(Rd, Rs1, Rs2),
30
31  // RV64A
32  LR_D(Rd, Rs1, AQ, RL),
33  SC_D(Rd, Rs1, Rs2, AQ, RL),
34  AMOSWAP_D(Rd, Rs1, Rs2, AQ, RL),
35  AMOADD_D(Rd, Rs1, Rs2, AQ, RL),
36  AMOXOR_D(Rd, Rs1, Rs2, AQ, RL),
37  AMOAND_D(Rd, Rs1, Rs2, AQ, RL),
38  AMOOR_D(Rd, Rs1, Rs2, AQ, RL),
39  AMOMIN_D(Rd, Rs1, Rs2, AQ, RL),
40  AMOMAX_D(Rd, Rs1, Rs2, AQ, RL),
41  AMOMINU_D(Rd, Rs1, Rs2, AQ, RL),
42  AMOMAXU_D(Rd, Rs1, Rs2, AQ, RL),
43
44  // RV64F
45  FCVT_L_S(Rd, Rs1, RoundingMode),
46  FCVT_LU_S(Rd, Rs1, RoundingMode),
47  FCVT_S_L(Rd, Rs1, RoundingMode),
48  FCVT_S_LU(Rd, Rs1, RoundingMode),
49
50  // RV64D
51  FCVT_L_D(Rd, Rs1, RoundingMode),
52  FCVT_LU_D(Rd, Rs1, RoundingMode),
53  FMV_X_D(Rd, Rs1),
54  FCVT_D_L(Rd, Rs1, RoundingMode),
55  FCVT_D_LU(Rd, Rs1, RoundingMode),
56  FMV_D_X(Rd, Rs1),
57
58  // RV32/64 Zicsr
59  CSRRW(Rd, Rs1, CSRAddr),
60  CSRRS(Rd, Rs1, CSRAddr),
61  CSRRC(Rd, Rs1, CSRAddr),
62  CSRRWI(Rd, UImm, CSRAddr),
63  CSRRSI(Rd, UImm, CSRAddr),
64  CSRRCI(Rd, UImm, CSRAddr),
65
66  // RV32/64 Zifencei
67  FENCE_I(Rd, Rs1, Imm32<11, 0>),
68
69  // Privileged
70  SRET,
71  MRET,
72  WFI,
73  SFENCE_VMA(Rs1, Rs2),
74  SINVAL_VMA(Rs1, Rs2),
75  SFENCE_W_INVAL,
76  SFENCE_INVAL_IR,
77}
78
79#[derive(Copy, Clone, Debug, Eq, PartialEq)]
80pub struct CSRAddr(pub Imm32<11, 0>);
81
82#[derive(Copy, Clone, Debug, Eq, PartialEq)]
83pub struct UImm(pub Imm32<4, 0>);
84
85impl CSRAddr {
86  pub fn value(self) -> u16 {
87    self.0.decode() as u16
88  }
89}
90
91impl UImm {
92  pub fn value(self) -> u32 {
93    self.0.decode()
94  }
95}
valheim_asm/isa/rv64.rs

valheim_asm/isa/
rv64.rs
