va416xx/
adc.rs

1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    ctrl: Ctrl,
5    fifo_data: FifoData,
6    status: Status,
7    irq_enb: IrqEnb,
8    irq_raw: IrqRaw,
9    irq_end: IrqEnd,
10    irq_clr: IrqClr,
11    rxfifoirqtrg: Rxfifoirqtrg,
12    fifo_clr: FifoClr,
13    _reserved9: [u8; 0x0fd8],
14    perid: Perid,
15}
16impl RegisterBlock {
17    #[doc = "0x00 - Control Register"]
18    #[inline(always)]
19    pub const fn ctrl(&self) -> &Ctrl {
20        &self.ctrl
21    }
22    #[doc = "0x04 - FIFO data"]
23    #[inline(always)]
24    pub const fn fifo_data(&self) -> &FifoData {
25        &self.fifo_data
26    }
27    #[doc = "0x08 - Status"]
28    #[inline(always)]
29    pub const fn status(&self) -> &Status {
30        &self.status
31    }
32    #[doc = "0x0c - Interrupt Enable"]
33    #[inline(always)]
34    pub const fn irq_enb(&self) -> &IrqEnb {
35        &self.irq_enb
36    }
37    #[doc = "0x10 - Raw Interrupt Status"]
38    #[inline(always)]
39    pub const fn irq_raw(&self) -> &IrqRaw {
40        &self.irq_raw
41    }
42    #[doc = "0x14 - Enabled Interrupt Status"]
43    #[inline(always)]
44    pub const fn irq_end(&self) -> &IrqEnd {
45        &self.irq_end
46    }
47    #[doc = "0x18 - Clear Interrupt"]
48    #[inline(always)]
49    pub const fn irq_clr(&self) -> &IrqClr {
50        &self.irq_clr
51    }
52    #[doc = "0x1c - Receive FIFO Interrupt Trigger Value"]
53    #[inline(always)]
54    pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg {
55        &self.rxfifoirqtrg
56    }
57    #[doc = "0x20 - FIFO Clear"]
58    #[inline(always)]
59    pub const fn fifo_clr(&self) -> &FifoClr {
60        &self.fifo_clr
61    }
62    #[doc = "0xffc - Peripheral ID Register"]
63    #[inline(always)]
64    pub const fn perid(&self) -> &Perid {
65        &self.perid
66    }
67}
68#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
69#[doc(alias = "CTRL")]
70pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
71#[doc = "Control Register"]
72pub mod ctrl;
73#[doc = "FIFO_DATA (r) register accessor: FIFO data\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`] module"]
74#[doc(alias = "FIFO_DATA")]
75pub type FifoData = crate::Reg<fifo_data::FifoDataSpec>;
76#[doc = "FIFO data"]
77pub mod fifo_data;
78#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
79#[doc(alias = "STATUS")]
80pub type Status = crate::Reg<status::StatusSpec>;
81#[doc = "Status"]
82pub mod status;
83#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
84#[doc(alias = "IRQ_ENB")]
85pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
86#[doc = "Interrupt Enable"]
87pub mod irq_enb;
88#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"]
89#[doc(alias = "IRQ_RAW")]
90pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
91#[doc = "Raw Interrupt Status"]
92pub mod irq_raw;
93#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"]
94#[doc(alias = "IRQ_END")]
95pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
96#[doc = "Enabled Interrupt Status"]
97pub mod irq_end;
98#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`] module"]
99#[doc(alias = "IRQ_CLR")]
100pub type IrqClr = crate::Reg<irq_clr::IrqClrSpec>;
101#[doc = "Clear Interrupt"]
102pub mod irq_clr;
103#[doc = "RXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
104#[doc(alias = "RXFIFOIRQTRG")]
105pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
106#[doc = "Receive FIFO Interrupt Trigger Value"]
107pub mod rxfifoirqtrg;
108#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
109#[doc(alias = "FIFO_CLR")]
110pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
111#[doc = "FIFO Clear"]
112pub mod fifo_clr;
113#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
114#[doc(alias = "PERID")]
115pub type Perid = crate::Reg<perid::PeridSpec>;
116#[doc = "Peripheral ID Register"]
117pub mod perid;