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#[cfg(feature = "embedded")]
use core::convert::Infallible;
#[cfg(feature = "embedded")]
use embedded_hal::serial;
#[cfg(feature = "embedded")]
use nb;
#[cfg(feature = "fmt")]
use core::fmt;
#[derive(Debug, Clone, PartialEq)]
pub enum ChipFifoInfo {
NoFifo,
Reserved,
EnabledNoFunction,
Enabled,
}
#[derive(Debug, Clone, PartialEq)]
pub enum InterruptType {
ModemStatus,
TransmitterHoldingRegisterEmpty,
ReceivedDataAvailable,
ReceiverLineStatus,
Timeout,
Reserved,
}
#[derive(Debug, Clone, PartialEq)]
pub enum Parity {
No,
Odd,
Even,
Mark,
Space,
}
pub struct MmioUart8250 {
base_address: usize,
}
impl MmioUart8250 {
pub fn new(base_address: usize) -> Self {
Self { base_address }
}
pub fn init(&self, clock: usize, baud_rate: usize) {
self.enable_divisor_latch_accessible();
let divisor = clock / (16 * baud_rate);
self.write_dll(divisor as u8);
self.write_dlh((divisor >> 8) as u8);
self.write_lcr(3);
self.write_fcr(1);
self.write_mcr(0);
self.enable_received_data_available_interrupt();
}
pub fn set_base_address(&mut self, base_address: usize) {
self.base_address = base_address;
}
pub fn read_byte(&self) -> Option<u8> {
if self.is_data_ready() {
Some(self.read_rbr())
} else {
None
}
}
pub fn write_byte(&self, byte: u8) {
self.write_thr(byte);
}
pub fn write_thr(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[0].write(value) }
}
pub fn read_rbr(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[0].read() }
}
pub fn read_dll(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[0].read() }
}
pub fn write_dll(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[0].write(value) }
}
pub fn read_dlh(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[1].read() }
}
pub fn write_dlh(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[1].write(value) }
}
pub fn set_divisor(&self, clock: usize, baud_rate: usize) {
if !self.is_divisor_latch_accessible() {
self.toggle_divisor_latch_accessible();
}
let divisor = clock / (16 * baud_rate);
self.write_dll(divisor as u8);
self.write_dlh((divisor >> 8) as u8);
self.toggle_divisor_latch_accessible();
}
pub fn read_ier(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[1].read() }
}
pub fn write_ier(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[1].write(value) }
}
pub fn is_low_power_mode_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[1].read() & 0b0010_0000 != 0 }
}
pub fn toggle_low_power_mode(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v ^ 0b0010_0000) }
}
pub fn enable_low_power_mode(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v | 0b0010_0000) }
}
pub fn disable_low_power_mode(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v & !0b0010_0000) }
}
pub fn is_sleep_mode_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[1].read() & 0b0001_0000 != 0 }
}
pub fn toggle_sleep_mode(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v ^ 0b0001_0000) }
}
pub fn enable_sleep_mode(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v | 0b0001_0000) }
}
pub fn disable_sleep_mode(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v & !0b0001_0000) }
}
pub fn is_modem_status_interrupt_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[1].read() & 0b0000_1000 != 0 }
}
pub fn toggle_modem_status_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v ^ 0b0000_1000) }
}
pub fn enable_modem_status_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v | 0b0000_1000) }
}
pub fn disable_modem_status_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v & !0b0000_1000) }
}
pub fn is_receiver_line_status_interrupt_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[1].read() & 0b0000_0100 != 0 }
}
pub fn toggle_receiver_line_status_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v ^ 0b0000_0100) }
}
pub fn enable_receiver_line_status_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v | 0b0000_0100) }
}
pub fn disable_receiver_line_status_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v & !0b0000_0100) }
}
pub fn is_transmitter_holding_register_empty_interrupt_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[1].read() & 0b0000_0010 != 0 }
}
pub fn toggle_transmitter_holding_register_empty_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v ^ 0b0000_0010) }
}
pub fn enable_transmitter_holding_register_empty_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v | 0b0000_0010) }
}
pub fn disable_transmitter_holding_register_empty_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v & !0b0000_0010) }
}
pub fn is_received_data_available_interrupt_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[1].read() & 0b0000_0001 != 0 }
}
pub fn toggle_received_data_available_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v ^ 0b0000_0001) }
}
pub fn enable_received_data_available_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v | 0b0000_0001) }
}
pub fn disable_received_data_available_interrupt(&self) {
unsafe { (*cast!(self.base_address)).rw[1].modify(|v| v & !0b0000_0001) }
}
pub fn read_iir(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[2].read() }
}
pub fn read_fifo_status(&self) -> ChipFifoInfo {
match unsafe { (*cast!(self.base_address)).rw[2].read() & 0b1100_0000 } {
0 => ChipFifoInfo::NoFifo,
0b0100_0000 => ChipFifoInfo::Reserved,
0b1000_0000 => ChipFifoInfo::EnabledNoFunction,
0b1100_0000 => ChipFifoInfo::Enabled,
_ => panic!("Can't reached"),
}
}
pub fn is_64byte_fifo_enabled(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[2].read() & 0b0010_0000 != 0 }
}
pub fn read_interrupt_type(&self) -> InterruptType {
match unsafe { (*cast!(self.base_address)).rw[2].read() & 0b0000_1110 } {
0 => InterruptType::ModemStatus,
0b0010 => InterruptType::TransmitterHoldingRegisterEmpty,
0b0100 => InterruptType::ReceivedDataAvailable,
0b0110 => InterruptType::ReceiverLineStatus,
0b1100 => InterruptType::Timeout,
0b1000 | 0b1010 | 0b1110 => InterruptType::Reserved,
_ => panic!("Can't reached"),
}
}
pub fn is_interrupt_pending(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[2].read() & 1 != 0 }
}
pub fn write_fcr(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[2].write(value) }
}
pub fn read_lcr(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[3].read() }
}
pub fn write_lcr(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[3].write(value) }
}
pub fn is_divisor_latch_accessible(&self) -> bool {
unsafe { (*cast!(self.base_address)).rw[3].read() & 0b1000_0000 != 0 }
}
pub fn toggle_divisor_latch_accessible(&self) {
unsafe { (*cast!(self.base_address)).rw[3].modify(|v| v ^ 0b1000_0000) }
}
pub fn enable_divisor_latch_accessible(&self) {
unsafe { (*cast!(self.base_address)).rw[3].modify(|v| v | 0b1000_0000) }
}
pub fn disable_divisor_latch_accessible(&self) {
unsafe { (*cast!(self.base_address)).rw[3].modify(|v| v & !0b1000_0000) }
}
pub fn get_parity(&self) -> Parity {
match unsafe { (*cast!(self.base_address)).rw[3].read() & 0b0011_1000 } {
0b0000_0000 => Parity::No,
0b0000_1000 => Parity::Odd,
0b0001_1000 => Parity::Even,
0b0010_1000 => Parity::Mark,
0b0011_1000 => Parity::Space,
_ => panic!("Invalid Parity! Please check your uart"),
}
}
pub fn set_parity(&self, parity: Parity) {
match parity {
Parity::No => unsafe {
(*cast!(self.base_address)).rw[3].modify(|v| (v & 0b1100_0111))
},
Parity::Odd => unsafe {
(*cast!(self.base_address)).rw[3].modify(|v| (v & 0b1100_0111) | 0b0000_1000)
},
Parity::Even => unsafe {
(*cast!(self.base_address)).rw[3].modify(|v| (v & 0b1100_0111) | 0b0001_1000)
},
Parity::Mark => unsafe {
(*cast!(self.base_address)).rw[3].modify(|v| (v & 0b1100_0111) | 0b0010_1000)
},
Parity::Space => unsafe {
(*cast!(self.base_address)).rw[3].modify(|v| v | 0b0011_1000)
},
}
}
pub fn get_stop_bit(&self) -> u8 {
((unsafe { (*cast!(self.base_address)).rw[3].read() & 0b100 }) >> 2) + 1
}
pub fn set_stop_bit(&self, stop_bit: u8) {
match stop_bit {
1 => unsafe { (*cast!(self.base_address)).rw[3].modify(|v| v & 0b1111_1011) },
2 => unsafe { (*cast!(self.base_address)).rw[3].modify(|v| v | 0b0000_0100) },
_ => panic!("Invalid stop bit"),
}
}
pub fn get_word_length(&self) -> u8 {
(unsafe { (*cast!(self.base_address)).rw[3].read() & 0b11 }) + 5
}
pub fn set_word_length(&self, length: u8) {
if (5..=8).contains(&length) {
unsafe { (*cast!(self.base_address)).rw[3].modify(|v| v | (length - 5)) }
} else {
panic!("Invalid word length")
}
}
pub fn read_mcr(&self) -> u8 {
unsafe { (*cast!(self.base_address)).rw[4].read() }
}
pub fn write_mcr(&self, value: u8) {
unsafe { (*cast!(self.base_address)).rw[4].write(value) }
}
pub fn read_lsr(&self) -> u8 {
unsafe { (*cast!(self.base_address)).ro[0].read() }
}
pub fn is_received_fifo_error(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b1000_0000 != 0 }
}
pub fn is_data_holding_registers_empty(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0100_0000 != 0 }
}
pub fn is_transmitter_holding_register_empty(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0010_0000 != 0 }
}
pub fn is_break_interrupt(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0001_0000 != 0 }
}
pub fn is_framing_error(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0000_1000 != 0 }
}
pub fn is_parity_error(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0000_0100 != 0 }
}
pub fn is_overrun_error(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0000_0010 != 0 }
}
pub fn is_data_ready(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[0].read() & 0b0000_0001 != 0 }
}
pub fn read_msr(&self) -> u8 {
unsafe { (*cast!(self.base_address)).ro[1].read() }
}
pub fn is_carrier_detect(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b1000_0000 != 0 }
}
pub fn is_ring_indicator(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0100_0000 != 0 }
}
pub fn is_data_set_ready(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0010_0000 != 0 }
}
pub fn is_clear_to_send(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0001_0000 != 0 }
}
pub fn is_delta_data_carrier_detect(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0000_1000 != 0 }
}
pub fn is_trailing_edge_ring_indicator(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0000_0100 != 0 }
}
pub fn is_delta_data_set_ready(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0000_0010 != 0 }
}
pub fn is_delta_clear_to_send(&self) -> bool {
unsafe { (*cast!(self.base_address)).ro[1].read() & 0b0000_0001 != 0 }
}
pub fn read_sr(&self) -> u8 {
unsafe { (*cast!(self.base_address)).scratch.read() }
}
pub fn write_sr(&self, value: u8) {
unsafe { (*cast!(self.base_address)).scratch.write(value) }
}
}
#[cfg(feature = "embedded")]
impl serial::Read<u8> for MmioUart8250 {
type Error = Infallible;
fn try_read(&mut self) -> nb::Result<u8, Self::Error> {
if self.is_interrupt_pending() {
Ok(self.read_rbr())
} else {
Err(nb::Error::WouldBlock)
}
}
}
#[cfg(feature = "embedded")]
impl serial::Write<u8> for MmioUart8250 {
type Error = Infallible;
fn try_write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
self.write_thr(word);
Ok(())
}
fn try_flush(&mut self) -> nb::Result<(), Self::Error> {
if self.is_interrupt_pending() {
Ok(())
} else {
Err(nb::Error::WouldBlock)
}
}
}
#[cfg(feature = "fmt")]
impl fmt::Write for MmioUart8250 {
fn write_str(&mut self, s: &str) -> fmt::Result {
for c in s.as_bytes() {
self.write_thr(*c);
}
Ok(())
}
}