Module target_features::docs::arm

Expand description

arm documentation

Features

Feature	Description	Also Enables^†
`aclass`	Is application profile (‘A’ series).
`aes`	Enable AES support.	`d32`, `neon`, `vfp2`, `vfp3`
`crc`	Enable support for CRC instructions.
`crypto`	Enable support for Cryptography extensions.	`aes`, `d32`, `neon`, `sha2`, `vfp2`, `vfp3`
`d32`	Extend FP to 32 double registers.
`dotprod`	Enable support for dot product instructions.	`d32`, `neon`, `vfp2`, `vfp3`
`dsp`	Supports DSP instructions in ARM and/or Thumb2.
`fp-armv8`	Enable ARMv8 FP.	`d32`, `vfp2`, `vfp3`, `vfp4`
`i8mm`	Enable Matrix Multiply Int8 Extension.	`d32`, `neon`, `vfp2`, `vfp3`
`mclass`	Is microcontroller profile (‘M’ series).
`neon`	Enable NEON instructions.	`d32`, `vfp2`, `vfp3`
`rclass`	Is realtime profile (‘R’ series).
`sha2`	Enable SHA1 and SHA256 support.	`d32`, `neon`, `vfp2`, `vfp3`
`thumb-mode`	Thumb mode.
`thumb2`	Enable Thumb2 instructions.
`v5te`	Support ARM v5TE, v5TEj, and v5TExp instructions.
`v6`	Support ARM v6 instructions.	`v5te`
`v6k`	Support ARM v6k instructions.	`v5te`, `v6`
`v6t2`	Support ARM v6t2 instructions.	`thumb2`, `v5te`, `v6`, `v6k`
`v7`	Support ARM v7 instructions.	`thumb2`, `v5te`, `v6`, `v6k`, `v6t2`
`v8`	Support ARM v8 instructions.	`thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`
`vfp2`	Enable VFP2 instructions.
`vfp3`	Enable VFP3 instructions.	`d32`, `vfp2`
`vfp4`	Enable VFP4 instructions.	`d32`, `vfp2`, `vfp3`
`crt-static`	Enables C Run-time Libraries to be statically linked.

^† This is often empirical, rather than specified in any standard, i.e. all available CPUs with a particular feature also have another feature.

CPUs

CPU	Enabled Features
`arm1020e`	`v5te`, `v6`, `vfp2`
`arm1020t`	`v5te`, `v6`, `vfp2`
`arm1022e`	`v5te`, `v6`, `vfp2`
`arm10e`	`v5te`, `v6`, `vfp2`
`arm10tdmi`	`v5te`, `v6`, `vfp2`
`arm1136j-s`	`dsp`, `v5te`, `v6`, `vfp2`
`arm1136jf-s`	`dsp`, `v5te`, `v6`, `vfp2`
`arm1156t2-s`	`dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `vfp2`
`arm1156t2f-s`	`dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `vfp2`
`arm1176jz-s`	`v5te`, `v6`, `v6k`, `vfp2`
`arm1176jzf-s`	`v5te`, `v6`, `v6k`, `vfp2`
`arm710t`	`v5te`, `v6`, `vfp2`
`arm720t`	`v5te`, `v6`, `vfp2`
`arm7tdmi`	`v5te`, `v6`, `vfp2`
`arm7tdmi-s`	`v5te`, `v6`, `vfp2`
`arm8`	`v5te`, `v6`, `vfp2`
`arm810`	`v5te`, `v6`, `vfp2`
`arm9`	`v5te`, `v6`, `vfp2`
`arm920`	`v5te`, `v6`, `vfp2`
`arm920t`	`v5te`, `v6`, `vfp2`
`arm922t`	`v5te`, `v6`, `vfp2`
`arm926ej-s`	`v5te`, `v6`, `vfp2`
`arm940t`	`v5te`, `v6`, `vfp2`
`arm946e-s`	`v5te`, `v6`, `vfp2`
`arm966e-s`	`v5te`, `v6`, `vfp2`
`arm968e-s`	`v5te`, `v6`, `vfp2`
`arm9e`	`v5te`, `v6`, `vfp2`
`arm9tdmi`	`v5te`, `v6`, `vfp2`
`cortex-a12`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-a15`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-a17`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-a32`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a35`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a5`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-a53`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a55`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a57`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a7`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-a710`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a72`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a73`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a75`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a76`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a76ae`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a77`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a78`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a78c`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-a8`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-a9`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m0`	`mclass`, `thumb-mode`, `v5te`, `v6`, `vfp2`
`cortex-m0plus`	`mclass`, `thumb-mode`, `v5te`, `v6`, `vfp2`
`cortex-m1`	`mclass`, `thumb-mode`, `v5te`, `v6`, `vfp2`
`cortex-m23`	`mclass`, `thumb-mode`, `v5te`, `v6`, `vfp2`
`cortex-m3`	`mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m33`	`dsp`, `mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m35p`	`dsp`, `mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m4`	`dsp`, `mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m55`	`dsp`, `mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m7`	`dsp`, `mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-m85`	`dsp`, `mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-r4`	`dsp`, `rclass`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-r4f`	`dsp`, `rclass`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-r5`	`dsp`, `rclass`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-r52`	`crc`, `dsp`, `rclass`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-r7`	`dsp`, `rclass`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-r8`	`dsp`, `rclass`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`cortex-x1`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cortex-x1c`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`cyclone`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`ep9312`	`v5te`, `v6`, `vfp2`
`exynos-m3`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`exynos-m4`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`exynos-m5`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`generic`	`v5te`, `v6`, `vfp2`
`iwmmxt`	`v5te`, `v6`, `vfp2`
`krait`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`kryo`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`mpcore`	`v5te`, `v6`, `v6k`, `vfp2`
`mpcorenovfp`	`v5te`, `v6`, `v6k`, `vfp2`
`neoverse-n1`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`neoverse-n2`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`neoverse-v1`	`aclass`, `crc`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `v8`, `vfp2`
`sc000`	`mclass`, `thumb-mode`, `v5te`, `v6`, `vfp2`
`sc300`	`mclass`, `thumb-mode`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`strongarm`	`v5te`, `v6`, `vfp2`
`strongarm110`	`v5te`, `v6`, `vfp2`
`strongarm1100`	`v5te`, `v6`, `vfp2`
`strongarm1110`	`v5te`, `v6`, `vfp2`
`swift`	`aclass`, `dsp`, `thumb2`, `v5te`, `v6`, `v6k`, `v6t2`, `v7`, `vfp2`
`xscale`	`v5te`, `v6`, `vfp2`