Expand description

Clock configuration register

Structs

Clock configuration register

Register CFGR reader

Register CFGR writer

Enums

HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)

HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)

Microcontroller clock output prescaler

Microcontroller clock output

PCLK1 prescaler flag (APB1)

PCLK1 low-speed prescaler (APB1)

PCLK2 prescaler flag (APB2)

PCLK2 high-speed prescaler (APB2)

Wakeup from Stop and CSS backup clock selection

System clock switch status

System clock switch

Type Definitions

Field HPREF reader - HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)

Field HPRE reader - HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)

Field HPRE writer - HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)

Field MCOPRE reader - Microcontroller clock output prescaler

Field MCOPRE writer - Microcontroller clock output prescaler

Field MCOSEL reader - Microcontroller clock output

Field MCOSEL writer - Microcontroller clock output

Field PPRE1F reader - PCLK1 prescaler flag (APB1)

Field PPRE1 reader - PCLK1 low-speed prescaler (APB1)

Field PPRE1 writer - PCLK1 low-speed prescaler (APB1)

Field PPRE2F reader - PCLK2 prescaler flag (APB2)

Field PPRE2 reader - PCLK2 high-speed prescaler (APB2)

Field PPRE2 writer - PCLK2 high-speed prescaler (APB2)

Field STOPWUCK reader - Wakeup from Stop and CSS backup clock selection

Field STOPWUCK writer - Wakeup from Stop and CSS backup clock selection

Field SWS reader - System clock switch status

Field SW reader - System clock switch

Field SW writer - System clock switch