Expand description
APB1 peripheral clocks enable in Sleep mode register 2
Re-exports
pub use LPUART1SMEN_A as LPTIM3SMEN_A;
pub use LPUART1SMEN_A as LPTIM2SMEN_A;
pub use LPUART1SMEN_R as LPTIM3SMEN_R;
pub use LPUART1SMEN_R as LPTIM2SMEN_R;
pub use LPUART1SMEN_W as LPTIM3SMEN_W;
pub use LPUART1SMEN_W as LPTIM2SMEN_W;
Structs
APB1 peripheral clocks enable in Sleep mode register 2
Register APB1SMENR2
reader
Register APB1SMENR2
writer
Enums
Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
Type Definitions
Field LPUART1SMEN
reader - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
Field LPUART1SMEN
writer - Low power UART 1 clock enable during CPU1 Csleep and CStop modes.