Module stm32wl::stm32wl5x_cm4::dbgmcu::c2apb1fzr2

source · [−]
Expand description

DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device

Structs

C2APB1FZR2_SPEC

DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device

R

Register C2APB1FZR2 reader

W

Register C2APB1FZR2 writer

Type Definitions

DBG_LPTIM2_STOP_R

Field DBG_LPTIM2_STOP reader - DBG_LPTIM2_STOP

DBG_LPTIM2_STOP_W

Field DBG_LPTIM2_STOP writer - DBG_LPTIM2_STOP

DBG_LPTIM3_STOP_R

Field DBG_LPTIM3_STOP reader - DBG_LPTIM3_STOP

DBG_LPTIM3_STOP_W

Field DBG_LPTIM3_STOP writer - DBG_LPTIM3_STOP