Module stm32wl::stm32wle5::usart1

source · [−]
Expand description

Universal synchronous asynchronous receiver transmitter

Modules

brr

baud rate register

cr1

control register 1

cr2

control register 2

cr3

control register 3

gtpr

guard time and prescaler register

icr

interrupt flag clear register

isr

interrupt and status register

presc

prescaler register

rdr

receive data register

rqr

request register

rtor

receiver timeout register

tdr

transmit data register

Structs

RegisterBlock

Register block

Type Definitions

BRR

BRR register accessor: an alias for Reg<BRR_SPEC>

CR1

CR1 register accessor: an alias for Reg<CR1_SPEC>

CR2

CR2 register accessor: an alias for Reg<CR2_SPEC>

CR3

CR3 register accessor: an alias for Reg<CR3_SPEC>

GTPR

GTPR register accessor: an alias for Reg<GTPR_SPEC>

ICR

ICR register accessor: an alias for Reg<ICR_SPEC>

ISR

ISR register accessor: an alias for Reg<ISR_SPEC>

PRESC

PRESC register accessor: an alias for Reg<PRESC_SPEC>

RDR

RDR register accessor: an alias for Reg<RDR_SPEC>

RQR

RQR register accessor: an alias for Reg<RQR_SPEC>

RTOR

RTOR register accessor: an alias for Reg<RTOR_SPEC>

TDR

TDR register accessor: an alias for Reg<TDR_SPEC>