Module stm32wl::stm32wle5::rcc [−][src]
Reset and clock control
Modules
| ahb1enr | AHB1 peripheral clock enable register |
| ahb1rstr | AHB1 peripheral reset register |
| ahb1smenr | AHB1 peripheral clocks enable in Sleep modes register |
| ahb2enr | AHB2 peripheral clock enable register |
| ahb2rstr | AHB2 peripheral reset register |
| ahb2smenr | AHB2 peripheral clocks enable in Sleep modes register |
| ahb3enr | AHB3 peripheral clock enable register |
| ahb3rstr | AHB3 peripheral reset register |
| ahb3smenr | AHB3 peripheral clocks enable in Sleep and Stop modes register |
| apb1enr1 | APB1 peripheral clock enable register 1 |
| apb1enr2 | APB1 peripheral clock enable register 2 |
| apb1rstr1 | APB1 peripheral reset register 1 |
| apb1rstr2 | APB1 peripheral reset register 2 |
| apb1smenr1 | APB1 peripheral clocks enable in Sleep mode register 1 |
| apb1smenr2 | APB1 peripheral clocks enable in Sleep mode register 2 |
| apb2enr | APB2 peripheral clock enable register |
| apb2rstr | APB2 peripheral reset register |
| apb2smenr | APB2 peripheral clocks enable in Sleep mode register |
| apb3enr | APB3 peripheral clock enable register |
| apb3rstr | APB3 peripheral reset register |
| apb3smenr | APB3 peripheral clock enable in Sleep mode register |
| bdcr | Backup domain control register |
| ccipr | Peripherals independent clock configuration register |
| cfgr | Clock configuration register |
| cicr | Clock interrupt clear register |
| cier | Clock interrupt enable register |
| cifr | Clock interrupt flag register |
| cr | Clock control register |
| csr | Control/status register |
| extcfgr | Extended clock recovery register |
| icscr | Internal clock sources calibration register |
| pllcfgr | PLL configuration register |
Structs
| RegisterBlock | Register block |
Type Definitions
| AHB1ENR | AHB1 peripheral clock enable register |
| AHB1RSTR | AHB1 peripheral reset register |
| AHB1SMENR | AHB1 peripheral clocks enable in Sleep modes register |
| AHB2ENR | AHB2 peripheral clock enable register |
| AHB2RSTR | AHB2 peripheral reset register |
| AHB2SMENR | AHB2 peripheral clocks enable in Sleep modes register |
| AHB3ENR | AHB3 peripheral clock enable register |
| AHB3RSTR | AHB3 peripheral reset register |
| AHB3SMENR | AHB3 peripheral clocks enable in Sleep and Stop modes register |
| APB1ENR1 | APB1 peripheral clock enable register 1 |
| APB1ENR2 | APB1 peripheral clock enable register 2 |
| APB1RSTR1 | APB1 peripheral reset register 1 |
| APB1RSTR2 | APB1 peripheral reset register 2 |
| APB1SMENR1 | APB1 peripheral clocks enable in Sleep mode register 1 |
| APB1SMENR2 | APB1 peripheral clocks enable in Sleep mode register 2 |
| APB2ENR | APB2 peripheral clock enable register |
| APB2RSTR | APB2 peripheral reset register |
| APB2SMENR | APB2 peripheral clocks enable in Sleep mode register |
| APB3ENR | APB3 peripheral clock enable register |
| APB3RSTR | APB3 peripheral reset register |
| APB3SMENR | APB3 peripheral clock enable in Sleep mode register |
| BDCR | Backup domain control register |
| CCIPR | Peripherals independent clock configuration register |
| CFGR | Clock configuration register |
| CICR | Clock interrupt clear register |
| CIER | Clock interrupt enable register |
| CIFR | Clock interrupt flag register |
| CR | Clock control register |
| CSR | Control/status register |
| EXTCFGR | Extended clock recovery register |
| ICSCR | Internal clock sources calibration register |
| PLLCFGR | PLL configuration register |