Module stm32wb::stm32wb55::syscfg::c2imr2

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Expand description

CPU2 interrupt mask register 1

Structs

C2IMR2_SPEC

CPU2 interrupt mask register 1

R

Register C2IMR2 reader

W

Register C2IMR2 writer

Type Definitions

DMA1_CH1_IM_R

Field DMA1_CH1_IM reader - Peripheral DMA1 CH1 interrupt mask to CPU2

DMA1_CH1_IM_W

Field DMA1_CH1_IM writer - Peripheral DMA1 CH1 interrupt mask to CPU2

DMA1_CH2_IM_R

Field DMA1_CH2_IM reader - Peripheral DMA1 CH2 interrupt mask to CPU2

DMA1_CH2_IM_W

Field DMA1_CH2_IM writer - Peripheral DMA1 CH2 interrupt mask to CPU2

DMA1_CH3_IM_R

Field DMA1_CH3_IM reader - Peripheral DMA1 CH3 interrupt mask to CPU2

DMA1_CH3_IM_W

Field DMA1_CH3_IM writer - Peripheral DMA1 CH3 interrupt mask to CPU2

DMA1_CH4_IM_R

Field DMA1_CH4_IM reader - Peripheral DMA1 CH4 interrupt mask to CPU2

DMA1_CH4_IM_W

Field DMA1_CH4_IM writer - Peripheral DMA1 CH4 interrupt mask to CPU2

DMA1_CH5_IM_R

Field DMA1_CH5_IM reader - Peripheral DMA1 CH5 interrupt mask to CPU2

DMA1_CH5_IM_W

Field DMA1_CH5_IM writer - Peripheral DMA1 CH5 interrupt mask to CPU2

DMA1_CH6_IM_R

Field DMA1_CH6_IM reader - Peripheral DMA1 CH6 interrupt mask to CPU2

DMA1_CH6_IM_W

Field DMA1_CH6_IM writer - Peripheral DMA1 CH6 interrupt mask to CPU2

DMA1_CH7_IM_R

Field DMA1_CH7_IM reader - Peripheral DMA1 CH7 interrupt mask to CPU2

DMA1_CH7_IM_W

Field DMA1_CH7_IM writer - Peripheral DMA1 CH7 interrupt mask to CPU2

DMA2_CH1_IM_R

Field DMA2_CH1_IM reader - Peripheral DMA2 CH1 interrupt mask to CPU1

DMA2_CH1_IM_W

Field DMA2_CH1_IM writer - Peripheral DMA2 CH1 interrupt mask to CPU1

DMA2_CH2_IM_R

Field DMA2_CH2_IM reader - Peripheral DMA2 CH2 interrupt mask to CPU1

DMA2_CH2_IM_W

Field DMA2_CH2_IM writer - Peripheral DMA2 CH2 interrupt mask to CPU1

DMA2_CH3_IM_R

Field DMA2_CH3_IM reader - Peripheral DMA2 CH3 interrupt mask to CPU1

DMA2_CH3_IM_W

Field DMA2_CH3_IM writer - Peripheral DMA2 CH3 interrupt mask to CPU1

DMA2_CH4_IM_R

Field DMA2_CH4_IM reader - Peripheral DMA2 CH4 interrupt mask to CPU1

DMA2_CH4_IM_W

Field DMA2_CH4_IM writer - Peripheral DMA2 CH4 interrupt mask to CPU1

DMA2_CH5_IM_R

Field DMA2_CH5_IM reader - Peripheral DMA2 CH5 interrupt mask to CPU1

DMA2_CH5_IM_W

Field DMA2_CH5_IM writer - Peripheral DMA2 CH5 interrupt mask to CPU1

DMA2_CH6_IM_R

Field DMA2_CH6_IM reader - Peripheral DMA2 CH6 interrupt mask to CPU1

DMA2_CH6_IM_W

Field DMA2_CH6_IM writer - Peripheral DMA2 CH6 interrupt mask to CPU1

DMA2_CH7_IM_R

Field DMA2_CH7_IM reader - Peripheral DMA2 CH7 interrupt mask to CPU1

DMA2_CH7_IM_W

Field DMA2_CH7_IM writer - Peripheral DMA2 CH7 interrupt mask to CPU1

DMAM_UX1_IM_R

Field DMAM_UX1_IM reader - Peripheral DMAM UX1 interrupt mask to CPU1

DMAM_UX1_IM_W

Field DMAM_UX1_IM writer - Peripheral DMAM UX1 interrupt mask to CPU1

LCDIM_R

Field LCDIM reader - Peripheral LCDIM interrupt mask to CPU1

LCDIM_W

Field LCDIM writer - Peripheral LCDIM interrupt mask to CPU1

PVDIM_R

Field PVDIM reader - Peripheral PVDIM interrupt mask to CPU1

PVDIM_W

Field PVDIM writer - Peripheral PVDIM interrupt mask to CPU1

PVM1IM_R

Field PVM1IM reader - Peripheral PVM1IM interrupt mask to CPU1

PVM1IM_W

Field PVM1IM writer - Peripheral PVM1IM interrupt mask to CPU1

PVM3IM_R

Field PVM3IM reader - Peripheral PVM3IM interrupt mask to CPU1

PVM3IM_W

Field PVM3IM writer - Peripheral PVM3IM interrupt mask to CPU1

TSCIM_R

Field TSCIM reader - Peripheral TSCIM interrupt mask to CPU1

TSCIM_W

Field TSCIM writer - Peripheral TSCIM interrupt mask to CPU1