Expand description
Mask register CPU2
Structs
Type Definitions
Field CH1FM
reader - processor 2 Transmit channel 1 free interrupt mask
Field CH1FM
writer - processor 2 Transmit channel 1 free interrupt mask
Field CH1OM
reader - processor 2 Receive channel 1 occupied interrupt enable
Field CH1OM
writer - processor 2 Receive channel 1 occupied interrupt enable
Field CH2FM
reader - processor 2 Transmit channel 2 free interrupt mask
Field CH2FM
writer - processor 2 Transmit channel 2 free interrupt mask
Field CH2OM
reader - processor 2 Receive channel 2 occupied interrupt enable
Field CH2OM
writer - processor 2 Receive channel 2 occupied interrupt enable
Field CH3FM
reader - processor 2 Transmit channel 3 free interrupt mask
Field CH3FM
writer - processor 2 Transmit channel 3 free interrupt mask
Field CH3OM
reader - processor 2 Receive channel 3 occupied interrupt enable
Field CH3OM
writer - processor 2 Receive channel 3 occupied interrupt enable
Field CH4FM
reader - processor 2 Transmit channel 4 free interrupt mask
Field CH4FM
writer - processor 2 Transmit channel 4 free interrupt mask
Field CH4OM
reader - processor 2 Receive channel 4 occupied interrupt enable
Field CH4OM
writer - processor 2 Receive channel 4 occupied interrupt enable
Field CH5FM
reader - processor 2 Transmit channel 5 free interrupt mask
Field CH5FM
writer - processor 2 Transmit channel 5 free interrupt mask
Field CH5OM
reader - processor 2 Receive channel 5 occupied interrupt enable
Field CH5OM
writer - processor 2 Receive channel 5 occupied interrupt enable
Field CH6FM
reader - processor 2 Transmit channel 6 free interrupt mask
Field CH6FM
writer - processor 2 Transmit channel 6 free interrupt mask
Field CH6OM
reader - processor 2 Receive channel 6 occupied interrupt enable
Field CH6OM
writer - processor 2 Receive channel 6 occupied interrupt enable