[][src]Type Definition stm32wb_pac::usart1::cr2::W

type W = W<u32, CR2>;

Writer for register CR2

Implementations

impl W[src]

pub fn add4_7(&mut self) -> ADD4_7_W<'_>[src]

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>[src]

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>[src]

Bit 23 - Receiver timeout enable

pub fn abrmod1(&mut self) -> ABRMOD1_W<'_>[src]

Bit 22 - Auto baud rate mode

pub fn abrmod0(&mut self) -> ABRMOD0_W<'_>[src]

Bit 21 - ABRMOD0

pub fn abren(&mut self) -> ABREN_W<'_>[src]

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>[src]

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>[src]

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>[src]

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>[src]

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>[src]

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>[src]

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>[src]

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>[src]

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>[src]

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>[src]

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>[src]

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>[src]

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>[src]

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>[src]

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>[src]

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>[src]

Bit 0 - Synchronous Slave mode enable