[][src]Type Definition stm32wb_pac::i2c1::isr::R

type R = R<u32, ISR>;

Reader of register ISR

Implementations

impl R[src]

pub fn addcode(&self) -> ADDCODE_R[src]

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R[src]

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R[src]

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R[src]

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R[src]

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R[src]

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R[src]

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R[src]

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R[src]

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R[src]

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R[src]

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R[src]

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R[src]

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R[src]

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R[src]

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R[src]

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R[src]

Bit 0 - Transmit data register empty (transmitters)