stm32ral/stm32wl/peripherals/flash.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Flash
4//!
5//! Used by: stm32wl5x_cm0p, stm32wl5x_cm4
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// Access control register
12pub mod ACR {
13
14 /// Latency
15 pub mod LATENCY {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (3 bits: 0b111 << 0)
19 pub const mask: u32 = 0b111 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b000: 0 wait states
28 pub const WS0: u32 = 0b000;
29
30 /// 0b001: 1 wait states
31 pub const WS1: u32 = 0b001;
32
33 /// 0b010: 2 wait states
34 pub const WS2: u32 = 0b010;
35 }
36 }
37
38 /// Prefetch enable
39 pub mod PRFTEN {
40 /// Offset (8 bits)
41 pub const offset: u32 = 8;
42 /// Mask (1 bit: 1 << 8)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: Prefetch is disabled
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: Prefetch is enabled
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Instruction cache enable
60 pub mod ICEN {
61 /// Offset (9 bits)
62 pub const offset: u32 = 9;
63 /// Mask (1 bit: 1 << 9)
64 pub const mask: u32 = 1 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b0: Instruction cache is disabled
73 pub const Disabled: u32 = 0b0;
74
75 /// 0b1: Instruction cache is enabled
76 pub const Enabled: u32 = 0b1;
77 }
78 }
79
80 /// Data cache enable
81 pub mod DCEN {
82 /// Offset (10 bits)
83 pub const offset: u32 = 10;
84 /// Mask (1 bit: 1 << 10)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values
91 pub mod RW {
92
93 /// 0b0: Data cache is disabled
94 pub const Disabled: u32 = 0b0;
95
96 /// 0b1: Data cache is enabled
97 pub const Enabled: u32 = 0b1;
98 }
99 }
100
101 /// Instruction cache reset
102 pub mod ICRST {
103 /// Offset (11 bits)
104 pub const offset: u32 = 11;
105 /// Mask (1 bit: 1 << 11)
106 pub const mask: u32 = 1 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b0: Instruction cache is not reset
115 pub const NotReset: u32 = 0b0;
116
117 /// 0b1: Instruction cache is reset
118 pub const Reset: u32 = 0b1;
119 }
120 }
121
122 /// Data cache reset
123 pub mod DCRST {
124 /// Offset (12 bits)
125 pub const offset: u32 = 12;
126 /// Mask (1 bit: 1 << 12)
127 pub const mask: u32 = 1 << offset;
128 /// Read-only values (empty)
129 pub mod R {}
130 /// Write-only values (empty)
131 pub mod W {}
132 /// Read-write values
133 pub mod RW {
134
135 /// 0b0: Data cache is not reset
136 pub const NotReset: u32 = 0b0;
137
138 /// 0b1: Data cache is reset
139 pub const Reset: u32 = 0b1;
140 }
141 }
142
143 /// CPU1 programm erase suspend request
144 pub mod PES {
145 /// Offset (15 bits)
146 pub const offset: u32 = 15;
147 /// Mask (1 bit: 1 << 15)
148 pub const mask: u32 = 1 << offset;
149 /// Read-only values (empty)
150 pub mod R {}
151 /// Write-only values (empty)
152 pub mod W {}
153 /// Read-write values
154 pub mod RW {
155
156 /// 0b0: Flash program and erase operations granted
157 pub const Granted: u32 = 0b0;
158
159 /// 0b1: Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACR is set
160 pub const Suspended: u32 = 0b1;
161 }
162 }
163
164 /// Flash User area empty
165 pub mod EMPTY {
166 /// Offset (16 bits)
167 pub const offset: u32 = 16;
168 /// Mask (1 bit: 1 << 16)
169 pub const mask: u32 = 1 << offset;
170 /// Read-only values (empty)
171 pub mod R {}
172 /// Write-only values (empty)
173 pub mod W {}
174 /// Read-write values
175 pub mod RW {
176
177 /// 0b0: User Flash programmend
178 pub const Programmed: u32 = 0b0;
179
180 /// 0b1: User Flash empty
181 pub const Empty: u32 = 0b1;
182 }
183 }
184}
185
186/// Flash access control register 2
187pub mod ACR2 {
188
189 /// CFI privileged mode enable
190 pub mod PRIVMODE {
191 /// Offset (0 bits)
192 pub const offset: u32 = 0;
193 /// Mask (1 bit: 1 << 0)
194 pub const mask: u32 = 1 << offset;
195 /// Read-only values (empty)
196 pub mod R {}
197 /// Write-only values (empty)
198 pub mod W {}
199 /// Read-write values (empty)
200 pub mod RW {}
201 }
202
203 /// Flash user hide protection area access disable
204 pub mod HDPADIS {
205 /// Offset (1 bits)
206 pub const offset: u32 = 1;
207 /// Mask (1 bit: 1 << 1)
208 pub const mask: u32 = 1 << offset;
209 /// Read-only values (empty)
210 pub mod R {}
211 /// Write-only values (empty)
212 pub mod W {}
213 /// Read-write values (empty)
214 pub mod RW {}
215 }
216
217 /// CPU2 Software debug enable
218 pub mod C2SWDBGEN {
219 /// Offset (2 bits)
220 pub const offset: u32 = 2;
221 /// Mask (1 bit: 1 << 2)
222 pub const mask: u32 = 1 << offset;
223 /// Read-only values (empty)
224 pub mod R {}
225 /// Write-only values (empty)
226 pub mod W {}
227 /// Read-write values (empty)
228 pub mod RW {}
229 }
230}
231
232/// Flash key register
233pub mod KEYR {
234
235 /// KEY
236 pub mod KEY {
237 /// Offset (0 bits)
238 pub const offset: u32 = 0;
239 /// Mask (32 bits: 0xffffffff << 0)
240 pub const mask: u32 = 0xffffffff << offset;
241 /// Read-only values (empty)
242 pub mod R {}
243 /// Write-only values (empty)
244 pub mod W {}
245 /// Read-write values (empty)
246 pub mod RW {}
247 }
248}
249
250/// Option byte key register
251pub mod OPTKEYR {
252
253 /// Option byte key
254 pub mod OPTKEY {
255 /// Offset (0 bits)
256 pub const offset: u32 = 0;
257 /// Mask (32 bits: 0xffffffff << 0)
258 pub const mask: u32 = 0xffffffff << offset;
259 /// Read-only values (empty)
260 pub mod R {}
261 /// Write-only values (empty)
262 pub mod W {}
263 /// Read-write values (empty)
264 pub mod RW {}
265 }
266}
267
268/// Status register
269pub mod SR {
270
271 /// End of operation
272 pub mod EOP {
273 /// Offset (0 bits)
274 pub const offset: u32 = 0;
275 /// Mask (1 bit: 1 << 0)
276 pub const mask: u32 = 1 << offset;
277 /// Read-only values
278 pub mod R {
279
280 /// 0b0: No EOP operation occurred
281 pub const NoEvent: u32 = 0b0;
282
283 /// 0b1: An EOP event occurred
284 pub const Event: u32 = 0b1;
285 }
286 /// Write-only values
287 pub mod W {
288
289 /// 0b1: Clear the flag
290 pub const Clear: u32 = 0b1;
291 }
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295
296 /// Operation error
297 pub mod OPERR {
298 /// Offset (1 bits)
299 pub const offset: u32 = 1;
300 /// Mask (1 bit: 1 << 1)
301 pub const mask: u32 = 1 << offset;
302 /// Read-only values
303 pub mod R {
304
305 /// 0b0: No memory opreation error happened
306 pub const NoError: u32 = 0b0;
307
308 /// 0b1: Memory operation error happened
309 pub const Error: u32 = 0b1;
310 }
311 pub use super::EOP::W;
312 /// Read-write values (empty)
313 pub mod RW {}
314 }
315
316 /// Programming error
317 pub mod PROGERR {
318 /// Offset (3 bits)
319 pub const offset: u32 = 3;
320 /// Mask (1 bit: 1 << 3)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values
323 pub mod R {
324
325 /// 0b0: No size programming error happened
326 pub const NoError: u32 = 0b0;
327
328 /// 0b1: Programming error happened
329 pub const Error: u32 = 0b1;
330 }
331 pub use super::EOP::W;
332 /// Read-write values (empty)
333 pub mod RW {}
334 }
335
336 /// Write protected error
337 pub mod WRPERR {
338 /// Offset (4 bits)
339 pub const offset: u32 = 4;
340 /// Mask (1 bit: 1 << 4)
341 pub const mask: u32 = 1 << offset;
342 /// Read-only values
343 pub mod R {
344
345 /// 0b0: No write protection error happened
346 pub const NoError: u32 = 0b0;
347
348 /// 0b1: Write protection error happened
349 pub const Error: u32 = 0b1;
350 }
351 pub use super::EOP::W;
352 /// Read-write values (empty)
353 pub mod RW {}
354 }
355
356 /// Programming alignment error
357 pub mod PGAERR {
358 /// Offset (5 bits)
359 pub const offset: u32 = 5;
360 /// Mask (1 bit: 1 << 5)
361 pub const mask: u32 = 1 << offset;
362 /// Read-only values
363 pub mod R {
364
365 /// 0b0: No programming alignment error happened
366 pub const NoError: u32 = 0b0;
367
368 /// 0b1: Programming alignment error happened
369 pub const Error: u32 = 0b1;
370 }
371 pub use super::EOP::W;
372 /// Read-write values (empty)
373 pub mod RW {}
374 }
375
376 /// Size error
377 pub mod SIZERR {
378 /// Offset (6 bits)
379 pub const offset: u32 = 6;
380 /// Mask (1 bit: 1 << 6)
381 pub const mask: u32 = 1 << offset;
382 /// Read-only values
383 pub mod R {
384
385 /// 0b0: No size error happened
386 pub const NoError: u32 = 0b0;
387
388 /// 0b1: Size error happened
389 pub const Error: u32 = 0b1;
390 }
391 pub use super::EOP::W;
392 /// Read-write values (empty)
393 pub mod RW {}
394 }
395
396 /// Programming sequence error
397 pub mod PGSERR {
398 /// Offset (7 bits)
399 pub const offset: u32 = 7;
400 /// Mask (1 bit: 1 << 7)
401 pub const mask: u32 = 1 << offset;
402 /// Read-only values
403 pub mod R {
404
405 /// 0b0: No fast programming sequence error happened
406 pub const NoError: u32 = 0b0;
407
408 /// 0b1: Fast programming sequence error happened
409 pub const Error: u32 = 0b1;
410 }
411 pub use super::EOP::W;
412 /// Read-write values (empty)
413 pub mod RW {}
414 }
415
416 /// Fast programming data miss error
417 pub mod MISSERR {
418 /// Offset (8 bits)
419 pub const offset: u32 = 8;
420 /// Mask (1 bit: 1 << 8)
421 pub const mask: u32 = 1 << offset;
422 /// Read-only values
423 pub mod R {
424
425 /// 0b0: No fast programming data miss error happened
426 pub const NoError: u32 = 0b0;
427
428 /// 0b1: Fast programming data miss error happened
429 pub const Error: u32 = 0b1;
430 }
431 pub use super::EOP::W;
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// Fast programming error
437 pub mod FASTERR {
438 /// Offset (9 bits)
439 pub const offset: u32 = 9;
440 /// Mask (1 bit: 1 << 9)
441 pub const mask: u32 = 1 << offset;
442 /// Read-only values
443 pub mod R {
444
445 /// 0b0: No fast programming error happened
446 pub const NoError: u32 = 0b0;
447
448 /// 0b1: Fast programming error happened
449 pub const Error: u32 = 0b1;
450 }
451 pub use super::EOP::W;
452 /// Read-write values (empty)
453 pub mod RW {}
454 }
455
456 /// User Option OPTIVAL indication
457 pub mod OPTNV {
458 /// Offset (13 bits)
459 pub const offset: u32 = 13;
460 /// Mask (1 bit: 1 << 13)
461 pub const mask: u32 = 1 << offset;
462 /// Read-only values
463 pub mod R {
464
465 /// 0b0: The OBL user option OPTVAL indicates "valid"
466 pub const Valid: u32 = 0b0;
467
468 /// 0b1: The OBL user option OPTVAL indicates "invalid"
469 pub const Invalid: u32 = 0b1;
470 }
471 /// Write-only values (empty)
472 pub mod W {}
473 /// Read-write values (empty)
474 pub mod RW {}
475 }
476
477 /// PCROP read error
478 pub mod RDERR {
479 /// Offset (14 bits)
480 pub const offset: u32 = 14;
481 /// Mask (1 bit: 1 << 14)
482 pub const mask: u32 = 1 << offset;
483 /// Read-only values
484 pub mod R {
485
486 /// 0b0: No read-only error happened
487 pub const NoError: u32 = 0b0;
488
489 /// 0b1: Read-only error happened
490 pub const Error: u32 = 0b1;
491 }
492 pub use super::EOP::W;
493 /// Read-write values (empty)
494 pub mod RW {}
495 }
496
497 /// Option validity error
498 pub mod OPTVERR {
499 /// Offset (15 bits)
500 pub const offset: u32 = 15;
501 /// Mask (1 bit: 1 << 15)
502 pub const mask: u32 = 1 << offset;
503 /// Read-only values
504 pub mod R {
505
506 /// 0b0: No error in option and engineering bits
507 pub const NoError: u32 = 0b0;
508
509 /// 0b1: Error in option and engineering bits
510 pub const Error: u32 = 0b1;
511 }
512 pub use super::EOP::W;
513 /// Read-write values (empty)
514 pub mod RW {}
515 }
516
517 /// Busy
518 pub mod BSY {
519 /// Offset (16 bits)
520 pub const offset: u32 = 16;
521 /// Mask (1 bit: 1 << 16)
522 pub const mask: u32 = 1 << offset;
523 /// Read-only values
524 pub mod R {
525
526 /// 0b0: No write/erase operation is in progress
527 pub const Inactive: u32 = 0b0;
528
529 /// 0b1: No write/erase operation is in progress
530 pub const Active: u32 = 0b1;
531 }
532 /// Write-only values (empty)
533 pub mod W {}
534 /// Read-write values (empty)
535 pub mod RW {}
536 }
537
538 /// Programming or erase configuration busy
539 pub mod CFGBSY {
540 /// Offset (18 bits)
541 pub const offset: u32 = 18;
542 /// Mask (1 bit: 1 << 18)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values
545 pub mod R {
546
547 /// 0b0: PG, PNB, PER, MER bits available for writing
548 pub const Free: u32 = 0b0;
549
550 /// 0b1: PG, PNB, PER, MER bits not available for writing (operation ongoing)
551 pub const Busy: u32 = 0b1;
552 }
553 /// Write-only values (empty)
554 pub mod W {}
555 /// Read-write values (empty)
556 pub mod RW {}
557 }
558
559 /// Programming / erase operation suspended
560 pub mod PESD {
561 /// Offset (19 bits)
562 pub const offset: u32 = 19;
563 /// Mask (1 bit: 1 << 19)
564 pub const mask: u32 = 1 << offset;
565 /// Read-only values
566 pub mod R {
567
568 /// 0b0: Flash program and erase operations granted
569 pub const Granted: u32 = 0b0;
570
571 /// 0b1: Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when the PES bit in FLASH_ACR is set
572 pub const Suspended: u32 = 0b1;
573 }
574 /// Write-only values (empty)
575 pub mod W {}
576 /// Read-write values (empty)
577 pub mod RW {}
578 }
579}
580
581/// Flash control register
582pub mod CR {
583
584 /// Programming
585 pub mod PG {
586 /// Offset (0 bits)
587 pub const offset: u32 = 0;
588 /// Mask (1 bit: 1 << 0)
589 pub const mask: u32 = 1 << offset;
590 /// Read-only values (empty)
591 pub mod R {}
592 /// Write-only values (empty)
593 pub mod W {}
594 /// Read-write values
595 pub mod RW {
596
597 /// 0b0: Flash programming disabled
598 pub const Disabled: u32 = 0b0;
599
600 /// 0b1: Flash programming enabled
601 pub const Enabled: u32 = 0b1;
602 }
603 }
604
605 /// Page erase
606 pub mod PER {
607 /// Offset (1 bits)
608 pub const offset: u32 = 1;
609 /// Mask (1 bit: 1 << 1)
610 pub const mask: u32 = 1 << offset;
611 /// Read-only values (empty)
612 pub mod R {}
613 /// Write-only values (empty)
614 pub mod W {}
615 /// Read-write values
616 pub mod RW {
617
618 /// 0b0: Page erase disabled
619 pub const Disabled: u32 = 0b0;
620
621 /// 0b1: Page erase enabled
622 pub const Enabled: u32 = 0b1;
623 }
624 }
625
626 /// Mass erase
627 pub mod MER {
628 /// Offset (2 bits)
629 pub const offset: u32 = 2;
630 /// Mask (1 bit: 1 << 2)
631 pub const mask: u32 = 1 << offset;
632 /// Read-only values (empty)
633 pub mod R {}
634 /// Write-only values (empty)
635 pub mod W {}
636 /// Read-write values
637 pub mod RW {
638
639 /// 0b0: No mass erase
640 pub const NoErase: u32 = 0b0;
641
642 /// 0b1: Trigger mass erase
643 pub const MassErase: u32 = 0b1;
644 }
645 }
646
647 /// Page number
648 pub mod PNB {
649 /// Offset (3 bits)
650 pub const offset: u32 = 3;
651 /// Mask (7 bits: 0x7f << 3)
652 pub const mask: u32 = 0x7f << offset;
653 /// Read-only values (empty)
654 pub mod R {}
655 /// Write-only values (empty)
656 pub mod W {}
657 /// Read-write values (empty)
658 pub mod RW {}
659 }
660
661 /// Start
662 pub mod STRT {
663 /// Offset (16 bits)
664 pub const offset: u32 = 16;
665 /// Mask (1 bit: 1 << 16)
666 pub const mask: u32 = 1 << offset;
667 /// Read-only values
668 pub mod R {
669
670 /// 0b0: Options modification completed or idle
671 pub const Done: u32 = 0b0;
672 }
673 /// Write-only values
674 pub mod W {
675
676 /// 0b1: Trigger options programming operation
677 pub const Start: u32 = 0b1;
678 }
679 /// Read-write values (empty)
680 pub mod RW {}
681 }
682
683 /// Options modification start
684 pub mod OPTSTRT {
685 /// Offset (17 bits)
686 pub const offset: u32 = 17;
687 /// Mask (1 bit: 1 << 17)
688 pub const mask: u32 = 1 << offset;
689 pub use super::STRT::R;
690 pub use super::STRT::W;
691 /// Read-write values (empty)
692 pub mod RW {}
693 }
694
695 /// Fast programming
696 pub mod FSTPG {
697 /// Offset (18 bits)
698 pub const offset: u32 = 18;
699 /// Mask (1 bit: 1 << 18)
700 pub const mask: u32 = 1 << offset;
701 /// Read-only values (empty)
702 pub mod R {}
703 /// Write-only values (empty)
704 pub mod W {}
705 /// Read-write values
706 pub mod RW {
707
708 /// 0b0: Fast programming disabled
709 pub const Disabled: u32 = 0b0;
710
711 /// 0b1: Fast programming enabled
712 pub const Enabled: u32 = 0b1;
713 }
714 }
715
716 /// End of operation interrupt enable
717 pub mod EOPIE {
718 /// Offset (24 bits)
719 pub const offset: u32 = 24;
720 /// Mask (1 bit: 1 << 24)
721 pub const mask: u32 = 1 << offset;
722 /// Read-only values (empty)
723 pub mod R {}
724 /// Write-only values (empty)
725 pub mod W {}
726 /// Read-write values
727 pub mod RW {
728
729 /// 0b0: End of program interrupt disable
730 pub const Disabled: u32 = 0b0;
731
732 /// 0b1: End of program interrupt enable
733 pub const Enabled: u32 = 0b1;
734 }
735 }
736
737 /// Error interrupt enable
738 pub mod ERRIE {
739 /// Offset (25 bits)
740 pub const offset: u32 = 25;
741 /// Mask (1 bit: 1 << 25)
742 pub const mask: u32 = 1 << offset;
743 /// Read-only values (empty)
744 pub mod R {}
745 /// Write-only values (empty)
746 pub mod W {}
747 /// Read-write values
748 pub mod RW {
749
750 /// 0b0: OPERR Error interrupt disable
751 pub const Disabled: u32 = 0b0;
752
753 /// 0b1: OPERR Error interrupt enable
754 pub const Enabled: u32 = 0b1;
755 }
756 }
757
758 /// PCROP read error interrupt enable
759 pub mod RDERRIE {
760 /// Offset (26 bits)
761 pub const offset: u32 = 26;
762 /// Mask (1 bit: 1 << 26)
763 pub const mask: u32 = 1 << offset;
764 /// Read-only values (empty)
765 pub mod R {}
766 /// Write-only values (empty)
767 pub mod W {}
768 /// Read-write values
769 pub mod RW {
770
771 /// 0b0: PCROP read error interrupt disable
772 pub const Disabled: u32 = 0b0;
773
774 /// 0b1: PCROP read error interrupt enable
775 pub const Enabled: u32 = 0b1;
776 }
777 }
778
779 /// Force the option byte loading
780 pub mod OBL_LAUNCH {
781 /// Offset (27 bits)
782 pub const offset: u32 = 27;
783 /// Mask (1 bit: 1 << 27)
784 pub const mask: u32 = 1 << offset;
785 /// Read-only values
786 pub mod R {
787
788 /// 0b0: Option byte loaded
789 pub const Complete: u32 = 0b0;
790
791 /// 0b1: Option byte loading to be done
792 pub const NotComplete: u32 = 0b1;
793 }
794 /// Write-only values
795 pub mod W {
796
797 /// 0b1: Reload option byte
798 pub const Reload: u32 = 0b1;
799 }
800 /// Read-write values (empty)
801 pub mod RW {}
802 }
803
804 /// Options Lock
805 pub mod OPTLOCK {
806 /// Offset (30 bits)
807 pub const offset: u32 = 30;
808 /// Mask (1 bit: 1 << 30)
809 pub const mask: u32 = 1 << offset;
810 /// Read-only values
811 pub mod R {
812
813 /// 0b0: FLASH_CR options are unlocked
814 pub const Unlocked: u32 = 0b0;
815 }
816 /// Write-only values
817 pub mod W {
818
819 /// 0b1: FLASH_CR options are locked
820 pub const Locked: u32 = 0b1;
821 }
822 /// Read-write values (empty)
823 pub mod RW {}
824 }
825
826 /// FLASH_CR Lock
827 pub mod LOCK {
828 /// Offset (31 bits)
829 pub const offset: u32 = 31;
830 /// Mask (1 bit: 1 << 31)
831 pub const mask: u32 = 1 << offset;
832 /// Read-only values
833 pub mod R {
834
835 /// 0b0: FLASH_CR is unlocked
836 pub const Unlocked: u32 = 0b0;
837 }
838 /// Write-only values
839 pub mod W {
840
841 /// 0b1: FLASH_CR is locked
842 pub const Locked: u32 = 0b1;
843 }
844 /// Read-write values (empty)
845 pub mod RW {}
846 }
847}
848
849/// Flash ECC register
850pub mod ECCR {
851
852 /// ECC fail address
853 pub mod ADDR_ECC {
854 /// Offset (0 bits)
855 pub const offset: u32 = 0;
856 /// Mask (17 bits: 0x1ffff << 0)
857 pub const mask: u32 = 0x1ffff << offset;
858 /// Read-only values (empty)
859 pub mod R {}
860 /// Write-only values (empty)
861 pub mod W {}
862 /// Read-write values (empty)
863 pub mod RW {}
864 }
865
866 /// System Flash ECC fail
867 pub mod SYSF_ECC {
868 /// Offset (20 bits)
869 pub const offset: u32 = 20;
870 /// Mask (1 bit: 1 << 20)
871 pub const mask: u32 = 1 << offset;
872 /// Read-only values
873 pub mod R {
874
875 /// 0b0: No System Flash memory ECC fail
876 pub const NotInFlash: u32 = 0b0;
877
878 /// 0b1: System Flash memory ECC fail
879 pub const InFlash: u32 = 0b1;
880 }
881 /// Write-only values (empty)
882 pub mod W {}
883 /// Read-write values (empty)
884 pub mod RW {}
885 }
886
887 /// ECC correction interrupt enable
888 pub mod ECCCIE {
889 /// Offset (24 bits)
890 pub const offset: u32 = 24;
891 /// Mask (1 bit: 1 << 24)
892 pub const mask: u32 = 1 << offset;
893 /// Read-only values (empty)
894 pub mod R {}
895 /// Write-only values (empty)
896 pub mod W {}
897 /// Read-write values
898 pub mod RW {
899
900 /// 0b0: ECCC interrupt disabled
901 pub const Disabled: u32 = 0b0;
902
903 /// 0b1: ECCC interrupt enabled
904 pub const Enabled: u32 = 0b1;
905 }
906 }
907
908 /// CPU identification
909 pub mod CPUID {
910 /// Offset (26 bits)
911 pub const offset: u32 = 26;
912 /// Mask (3 bits: 0b111 << 26)
913 pub const mask: u32 = 0b111 << offset;
914 /// Read-only values (empty)
915 pub mod R {}
916 /// Write-only values (empty)
917 pub mod W {}
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// ECC correction
923 pub mod ECCC {
924 /// Offset (30 bits)
925 pub const offset: u32 = 30;
926 /// Mask (1 bit: 1 << 30)
927 pub const mask: u32 = 1 << offset;
928 /// Read-only values
929 pub mod R {
930
931 /// 0b0: ECC error corrected
932 pub const NoEvent: u32 = 0b0;
933
934 /// 0b1: No ECC error corrected
935 pub const Event: u32 = 0b1;
936 }
937 /// Write-only values
938 pub mod W {
939
940 /// 0b1: Clear the flag
941 pub const Clear: u32 = 0b1;
942 }
943 /// Read-write values (empty)
944 pub mod RW {}
945 }
946
947 /// ECC detection
948 pub mod ECCD {
949 /// Offset (31 bits)
950 pub const offset: u32 = 31;
951 /// Mask (1 bit: 1 << 31)
952 pub const mask: u32 = 1 << offset;
953 /// Read-only values
954 pub mod R {
955
956 /// 0b0: Two ECC errors detected
957 pub const NoEvent: u32 = 0b0;
958
959 /// 0b1: No two ECC errors detected
960 pub const Event: u32 = 0b1;
961 }
962 pub use super::ECCC::W;
963 /// Read-write values (empty)
964 pub mod RW {}
965 }
966}
967
968/// Flash option register
969pub mod OPTR {
970
971 /// Read protection level
972 pub mod RDP {
973 /// Offset (0 bits)
974 pub const offset: u32 = 0;
975 /// Mask (8 bits: 0xff << 0)
976 pub const mask: u32 = 0xff << offset;
977 /// Read-only values (empty)
978 pub mod R {}
979 /// Write-only values (empty)
980 pub mod W {}
981 /// Read-write values
982 pub mod RW {
983
984 /// 0b10001000: Level 1, memories readout protection active (writes 0x88)
985 pub const Level1: u32 = 0b10001000;
986
987 /// 0b10101010: Level 0, readout protection not active
988 pub const Level0: u32 = 0b10101010;
989
990 /// 0b11001100: Level 2, chip readout protection active
991 pub const Level2: u32 = 0b11001100;
992 }
993 }
994
995 /// System security enabled flag
996 pub mod ESE {
997 /// Offset (8 bits)
998 pub const offset: u32 = 8;
999 /// Mask (1 bit: 1 << 8)
1000 pub const mask: u32 = 1 << offset;
1001 /// Read-only values (empty)
1002 pub mod R {}
1003 /// Write-only values (empty)
1004 pub mod W {}
1005 /// Read-write values
1006 pub mod RW {
1007
1008 /// 0b0: Security disabled
1009 pub const Disabled: u32 = 0b0;
1010
1011 /// 0b1: Security enabled
1012 pub const Enabled: u32 = 0b1;
1013 }
1014 }
1015
1016 /// BOR reset Level
1017 pub mod BOR_LEV {
1018 /// Offset (9 bits)
1019 pub const offset: u32 = 9;
1020 /// Mask (3 bits: 0b111 << 9)
1021 pub const mask: u32 = 0b111 << offset;
1022 /// Read-only values (empty)
1023 pub mod R {}
1024 /// Write-only values (empty)
1025 pub mod W {}
1026 /// Read-write values
1027 pub mod RW {
1028
1029 /// 0b000: BOR level 0. Reset level threshold is around 1.7 V
1030 pub const Level0: u32 = 0b000;
1031
1032 /// 0b001: BOR level 1. Reset level threshold is around 2.0 V
1033 pub const Level1: u32 = 0b001;
1034
1035 /// 0b010: BOR level 2. Reset level threshold is around 2.2 V
1036 pub const Level2: u32 = 0b010;
1037
1038 /// 0b011: BOR level 3. Reset level threshold is around 2.5 V
1039 pub const Level3: u32 = 0b011;
1040
1041 /// 0b100: BOR level 4. Reset level threshold is around 2.8 V
1042 pub const Level4: u32 = 0b100;
1043 }
1044 }
1045
1046 /// nRST_STOP
1047 pub mod nRST_STOP {
1048 /// Offset (12 bits)
1049 pub const offset: u32 = 12;
1050 /// Mask (1 bit: 1 << 12)
1051 pub const mask: u32 = 1 << offset;
1052 /// Read-only values (empty)
1053 pub mod R {}
1054 /// Write-only values (empty)
1055 pub mod W {}
1056 /// Read-write values
1057 pub mod RW {
1058
1059 /// 0b0: Reset generated when entering the Standby mode
1060 pub const Enabled: u32 = 0b0;
1061
1062 /// 0b1: No reset generated when entering the Standby mode
1063 pub const Disabled: u32 = 0b1;
1064 }
1065 }
1066
1067 /// nRST_STDBY
1068 pub mod nRST_STDBY {
1069 /// Offset (13 bits)
1070 pub const offset: u32 = 13;
1071 /// Mask (1 bit: 1 << 13)
1072 pub const mask: u32 = 1 << offset;
1073 /// Read-only values (empty)
1074 pub mod R {}
1075 /// Write-only values (empty)
1076 pub mod W {}
1077 pub use super::nRST_STOP::RW;
1078 }
1079
1080 /// nRSTSHDW
1081 pub mod nRST_SHDW {
1082 /// Offset (14 bits)
1083 pub const offset: u32 = 14;
1084 /// Mask (1 bit: 1 << 14)
1085 pub const mask: u32 = 1 << offset;
1086 /// Read-only values (empty)
1087 pub mod R {}
1088 /// Write-only values (empty)
1089 pub mod W {}
1090 /// Read-write values
1091 pub mod RW {
1092
1093 /// 0b0: Reset generated when entering the Shutdown mode
1094 pub const Enabled: u32 = 0b0;
1095
1096 /// 0b1: No reset generated when entering the Shutdown mode
1097 pub const Disabled: u32 = 0b1;
1098 }
1099 }
1100
1101 /// Independent watchdog selection
1102 pub mod IWDG_SW {
1103 /// Offset (16 bits)
1104 pub const offset: u32 = 16;
1105 /// Mask (1 bit: 1 << 16)
1106 pub const mask: u32 = 1 << offset;
1107 /// Read-only values (empty)
1108 pub mod R {}
1109 /// Write-only values (empty)
1110 pub mod W {}
1111 /// Read-write values
1112 pub mod RW {
1113
1114 /// 0b0: Hardware independent watchdog
1115 pub const Hardware: u32 = 0b0;
1116
1117 /// 0b1: Software independent watchdog
1118 pub const Software: u32 = 0b1;
1119 }
1120 }
1121
1122 /// Independent watchdog counter freeze in Stop mode
1123 pub mod IWDG_STOP {
1124 /// Offset (17 bits)
1125 pub const offset: u32 = 17;
1126 /// Mask (1 bit: 1 << 17)
1127 pub const mask: u32 = 1 << offset;
1128 /// Read-only values (empty)
1129 pub mod R {}
1130 /// Write-only values (empty)
1131 pub mod W {}
1132 /// Read-write values
1133 pub mod RW {
1134
1135 /// 0b0: Independent watchdog counter frozen in Stop mode
1136 pub const Frozen: u32 = 0b0;
1137
1138 /// 0b1: Independent watchdog counter running in Stop mode
1139 pub const Running: u32 = 0b1;
1140 }
1141 }
1142
1143 /// Independent watchdog counter freeze in Standby mode
1144 pub mod IWDG_STDBY {
1145 /// Offset (18 bits)
1146 pub const offset: u32 = 18;
1147 /// Mask (1 bit: 1 << 18)
1148 pub const mask: u32 = 1 << offset;
1149 /// Read-only values (empty)
1150 pub mod R {}
1151 /// Write-only values (empty)
1152 pub mod W {}
1153 /// Read-write values
1154 pub mod RW {
1155
1156 /// 0b0: Independent watchdog counter frozen in Standby mode
1157 pub const Frozen: u32 = 0b0;
1158
1159 /// 0b1: Independent watchdog counter running in Standby mode
1160 pub const Running: u32 = 0b1;
1161 }
1162 }
1163
1164 /// Window watchdog selection
1165 pub mod WWDG_SW {
1166 /// Offset (19 bits)
1167 pub const offset: u32 = 19;
1168 /// Mask (1 bit: 1 << 19)
1169 pub const mask: u32 = 1 << offset;
1170 /// Read-only values (empty)
1171 pub mod R {}
1172 /// Write-only values (empty)
1173 pub mod W {}
1174 /// Read-write values
1175 pub mod RW {
1176
1177 /// 0b0: Hardware window watchdog
1178 pub const Hardware: u32 = 0b0;
1179
1180 /// 0b1: Software window watchdog
1181 pub const Software: u32 = 0b1;
1182 }
1183 }
1184
1185 /// Boot configuration
1186 pub mod nBOOT1 {
1187 /// Offset (23 bits)
1188 pub const offset: u32 = 23;
1189 /// Mask (1 bit: 1 << 23)
1190 pub const mask: u32 = 1 << offset;
1191 /// Read-only values (empty)
1192 pub mod R {}
1193 /// Write-only values (empty)
1194 pub mod W {}
1195 /// Read-write values
1196 pub mod RW {
1197
1198 /// 0b0: When nSWBOOT0 is cleared, select boot mode together with nBOOT0
1199 pub const Clear: u32 = 0b0;
1200
1201 /// 0b1: When nSWBOOT0 is cleared, select boot mode together with nBOOT0
1202 pub const Set: u32 = 0b1;
1203 }
1204 }
1205
1206 /// SRAM2 parity check enable
1207 pub mod SRAM2_PE {
1208 /// Offset (24 bits)
1209 pub const offset: u32 = 24;
1210 /// Mask (1 bit: 1 << 24)
1211 pub const mask: u32 = 1 << offset;
1212 /// Read-only values (empty)
1213 pub mod R {}
1214 /// Write-only values (empty)
1215 pub mod W {}
1216 /// Read-write values
1217 pub mod RW {
1218
1219 /// 0b0: SRAM2 Parity check enabled
1220 pub const Enabled: u32 = 0b0;
1221
1222 /// 0b1: SRAM2 Parity check disabled
1223 pub const Disabled: u32 = 0b1;
1224 }
1225 }
1226
1227 /// SRAM2 Erase when system reset
1228 pub mod SRAM_RST {
1229 /// Offset (25 bits)
1230 pub const offset: u32 = 25;
1231 /// Mask (1 bit: 1 << 25)
1232 pub const mask: u32 = 1 << offset;
1233 /// Read-only values (empty)
1234 pub mod R {}
1235 /// Write-only values (empty)
1236 pub mod W {}
1237 /// Read-write values
1238 pub mod RW {
1239
1240 /// 0b0: SRAM1 and SRAM2 erased when a system reset occurs
1241 pub const Reset: u32 = 0b0;
1242
1243 /// 0b1: SRAM1 and SRAM2 not erased when a system reset occurs
1244 pub const NotReset: u32 = 0b1;
1245 }
1246 }
1247
1248 /// Software BOOT0 selection
1249 pub mod nSWBOOT0 {
1250 /// Offset (26 bits)
1251 pub const offset: u32 = 26;
1252 /// Mask (1 bit: 1 << 26)
1253 pub const mask: u32 = 1 << offset;
1254 /// Read-only values (empty)
1255 pub mod R {}
1256 /// Write-only values (empty)
1257 pub mod W {}
1258 /// Read-write values
1259 pub mod RW {
1260
1261 /// 0b0: BOOT0 taken from nBOOT0 in this register
1262 pub const Bit: u32 = 0b0;
1263
1264 /// 0b1: BOOT0 taken from GPIO PH3/BOOT0
1265 pub const Pin: u32 = 0b1;
1266 }
1267 }
1268
1269 /// nBOOT0 option bit
1270 pub mod nBOOT0 {
1271 /// Offset (27 bits)
1272 pub const offset: u32 = 27;
1273 /// Mask (1 bit: 1 << 27)
1274 pub const mask: u32 = 1 << offset;
1275 /// Read-only values (empty)
1276 pub mod R {}
1277 /// Write-only values (empty)
1278 pub mod W {}
1279 /// Read-write values
1280 pub mod RW {
1281
1282 /// 0b0: When nSWBOOT0 is cleared, select boot mode together with nBOOT1
1283 pub const Clear: u32 = 0b0;
1284
1285 /// 0b1: When nSWBOOT0 is cleared, select boot mode together with nBOOT1
1286 pub const Set: u32 = 0b1;
1287 }
1288 }
1289
1290 /// CPU1 CM4 Unique Boot entry enable option bit
1291 pub mod BOOT_LOCK {
1292 /// Offset (30 bits)
1293 pub const offset: u32 = 30;
1294 /// Mask (1 bit: 1 << 30)
1295 pub const mask: u32 = 1 << offset;
1296 /// Read-only values (empty)
1297 pub mod R {}
1298 /// Write-only values (empty)
1299 pub mod W {}
1300 /// Read-write values
1301 pub mod RW {
1302
1303 /// 0b0: Boot lock is disabled
1304 pub const Disabled: u32 = 0b0;
1305
1306 /// 0b1: Boot lock is enabled
1307 pub const Enabled: u32 = 0b1;
1308 }
1309 }
1310
1311 /// CPU2 CM0+ Unique Boot entry enable option bit
1312 pub mod C2BOOT_LOCK {
1313 /// Offset (31 bits)
1314 pub const offset: u32 = 31;
1315 /// Mask (1 bit: 1 << 31)
1316 pub const mask: u32 = 1 << offset;
1317 /// Read-only values (empty)
1318 pub mod R {}
1319 /// Write-only values (empty)
1320 pub mod W {}
1321 /// Read-write values (empty)
1322 pub mod RW {}
1323 }
1324}
1325
1326/// Flash PCROP zone A Start address register
1327pub mod PCROP1ASR {
1328
1329 /// PCROP1A area start offset
1330 pub mod PCROP1A_STRT {
1331 /// Offset (0 bits)
1332 pub const offset: u32 = 0;
1333 /// Mask (8 bits: 0xff << 0)
1334 pub const mask: u32 = 0xff << offset;
1335 /// Read-only values (empty)
1336 pub mod R {}
1337 /// Write-only values (empty)
1338 pub mod W {}
1339 /// Read-write values (empty)
1340 pub mod RW {}
1341 }
1342}
1343
1344/// Flash PCROP zone A End address register
1345pub mod PCROP1AER {
1346
1347 /// PCROP area end offset
1348 pub mod PCROP1A_END {
1349 /// Offset (0 bits)
1350 pub const offset: u32 = 0;
1351 /// Mask (8 bits: 0xff << 0)
1352 pub const mask: u32 = 0xff << offset;
1353 /// Read-only values (empty)
1354 pub mod R {}
1355 /// Write-only values (empty)
1356 pub mod W {}
1357 /// Read-write values (empty)
1358 pub mod RW {}
1359 }
1360
1361 /// PCROP area preserved when RDP level decreased
1362 pub mod PCROP_RDP {
1363 /// Offset (31 bits)
1364 pub const offset: u32 = 31;
1365 /// Mask (1 bit: 1 << 31)
1366 pub const mask: u32 = 1 << offset;
1367 /// Read-only values (empty)
1368 pub mod R {}
1369 /// Write-only values (empty)
1370 pub mod W {}
1371 /// Read-write values (empty)
1372 pub mod RW {}
1373 }
1374}
1375
1376/// Flash WRP area A address register
1377pub mod WRP1AR {
1378
1379 /// Bank 1 WRP first area start offset
1380 pub mod WRP1A_STRT {
1381 /// Offset (0 bits)
1382 pub const offset: u32 = 0;
1383 /// Mask (7 bits: 0x7f << 0)
1384 pub const mask: u32 = 0x7f << offset;
1385 /// Read-only values (empty)
1386 pub mod R {}
1387 /// Write-only values (empty)
1388 pub mod W {}
1389 /// Read-write values (empty)
1390 pub mod RW {}
1391 }
1392
1393 /// Bank 1 WRP first area A end offset
1394 pub mod WRP1A_END {
1395 /// Offset (16 bits)
1396 pub const offset: u32 = 16;
1397 /// Mask (7 bits: 0x7f << 16)
1398 pub const mask: u32 = 0x7f << offset;
1399 /// Read-only values (empty)
1400 pub mod R {}
1401 /// Write-only values (empty)
1402 pub mod W {}
1403 /// Read-write values (empty)
1404 pub mod RW {}
1405 }
1406}
1407
1408/// Flash WRP area B address register
1409pub mod WRP1BR {
1410
1411 /// Bank 1 WRP second area B end offset
1412 pub mod WRP1B_STRT {
1413 /// Offset (0 bits)
1414 pub const offset: u32 = 0;
1415 /// Mask (7 bits: 0x7f << 0)
1416 pub const mask: u32 = 0x7f << offset;
1417 /// Read-only values (empty)
1418 pub mod R {}
1419 /// Write-only values (empty)
1420 pub mod W {}
1421 /// Read-write values (empty)
1422 pub mod RW {}
1423 }
1424
1425 /// Bank 1 WRP second area B start offset
1426 pub mod WRP1B_END {
1427 /// Offset (16 bits)
1428 pub const offset: u32 = 16;
1429 /// Mask (7 bits: 0x7f << 16)
1430 pub const mask: u32 = 0x7f << offset;
1431 /// Read-only values (empty)
1432 pub mod R {}
1433 /// Write-only values (empty)
1434 pub mod W {}
1435 /// Read-write values (empty)
1436 pub mod RW {}
1437 }
1438}
1439
1440/// Flash PCROP zone B Start address register
1441pub mod PCROP1BSR {
1442
1443 /// Bank 1 WRP second area B end offset
1444 pub mod PCROP1B_STRT {
1445 /// Offset (0 bits)
1446 pub const offset: u32 = 0;
1447 /// Mask (8 bits: 0xff << 0)
1448 pub const mask: u32 = 0xff << offset;
1449 /// Read-only values (empty)
1450 pub mod R {}
1451 /// Write-only values (empty)
1452 pub mod W {}
1453 /// Read-write values (empty)
1454 pub mod RW {}
1455 }
1456}
1457
1458/// Flash PCROP zone B End address register
1459pub mod PCROP1BER {
1460
1461 /// PCROP1B area end offset
1462 pub mod PCROP1B_END {
1463 /// Offset (0 bits)
1464 pub const offset: u32 = 0;
1465 /// Mask (8 bits: 0xff << 0)
1466 pub const mask: u32 = 0xff << offset;
1467 /// Read-only values (empty)
1468 pub mod R {}
1469 /// Write-only values (empty)
1470 pub mod W {}
1471 /// Read-write values (empty)
1472 pub mod RW {}
1473 }
1474}
1475
1476/// Flash IPCC data buffer address register
1477pub mod IPCCBR {
1478
1479 /// IPCCDBA
1480 pub mod IPCCDBA {
1481 /// Offset (0 bits)
1482 pub const offset: u32 = 0;
1483 /// Mask (14 bits: 0x3fff << 0)
1484 pub const mask: u32 = 0x3fff << offset;
1485 /// Read-only values (empty)
1486 pub mod R {}
1487 /// Write-only values (empty)
1488 pub mod W {}
1489 /// Read-write values (empty)
1490 pub mod RW {}
1491 }
1492}
1493
1494/// Flash CPU2 access control register
1495pub mod C2ACR {
1496
1497 /// CPU2 Prefetch enable
1498 pub mod PRFTEN {
1499 /// Offset (8 bits)
1500 pub const offset: u32 = 8;
1501 /// Mask (1 bit: 1 << 8)
1502 pub const mask: u32 = 1 << offset;
1503 /// Read-only values (empty)
1504 pub mod R {}
1505 /// Write-only values (empty)
1506 pub mod W {}
1507 /// Read-write values
1508 pub mod RW {
1509
1510 /// 0b0: CPU2 prefetch is disabled
1511 pub const Disabled: u32 = 0b0;
1512
1513 /// 0b1: CPU2 prefetch is enabled
1514 pub const Enabled: u32 = 0b1;
1515 }
1516 }
1517
1518 /// CPU2 Instruction cache enable
1519 pub mod ICEN {
1520 /// Offset (9 bits)
1521 pub const offset: u32 = 9;
1522 /// Mask (1 bit: 1 << 9)
1523 pub const mask: u32 = 1 << offset;
1524 /// Read-only values (empty)
1525 pub mod R {}
1526 /// Write-only values (empty)
1527 pub mod W {}
1528 /// Read-write values
1529 pub mod RW {
1530
1531 /// 0b0: CPU2 instruction cache is disabled
1532 pub const Disabled: u32 = 0b0;
1533
1534 /// 0b1: CPU2 instruction cache is enabled
1535 pub const Enabled: u32 = 0b1;
1536 }
1537 }
1538
1539 /// CPU2 Instruction cache reset
1540 pub mod ICRST {
1541 /// Offset (11 bits)
1542 pub const offset: u32 = 11;
1543 /// Mask (1 bit: 1 << 11)
1544 pub const mask: u32 = 1 << offset;
1545 /// Read-only values (empty)
1546 pub mod R {}
1547 /// Write-only values (empty)
1548 pub mod W {}
1549 /// Read-write values
1550 pub mod RW {
1551
1552 /// 0b0: CPU2 instruction cache is not reset
1553 pub const NotReset: u32 = 0b0;
1554
1555 /// 0b1: CPU2 instruction cache is reset
1556 pub const Reset: u32 = 0b1;
1557 }
1558 }
1559
1560 /// CPU2 program / erase suspend request
1561 pub mod PES {
1562 /// Offset (15 bits)
1563 pub const offset: u32 = 15;
1564 /// Mask (1 bit: 1 << 15)
1565 pub const mask: u32 = 1 << offset;
1566 /// Read-only values (empty)
1567 pub mod R {}
1568 /// Write-only values (empty)
1569 pub mod W {}
1570 /// Read-write values
1571 pub mod RW {
1572
1573 /// 0b0: Flash program and erase operations granted
1574 pub const Granted: u32 = 0b0;
1575
1576 /// 0b1: Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_C2SR is set when PES bit in FLASH_C2ACR is set
1577 pub const Suspended: u32 = 0b1;
1578 }
1579 }
1580}
1581
1582/// Flash CPU2 status register
1583pub mod C2SR {
1584
1585 /// End of operation
1586 pub mod EOP {
1587 /// Offset (0 bits)
1588 pub const offset: u32 = 0;
1589 /// Mask (1 bit: 1 << 0)
1590 pub const mask: u32 = 1 << offset;
1591 /// Read-only values
1592 pub mod R {
1593
1594 /// 0b0: No EOP operation occurred
1595 pub const NoEvent: u32 = 0b0;
1596
1597 /// 0b1: An EOP event occurred
1598 pub const Event: u32 = 0b1;
1599 }
1600 /// Write-only values
1601 pub mod W {
1602
1603 /// 0b1: Clear the flag
1604 pub const Clear: u32 = 0b1;
1605 }
1606 /// Read-write values (empty)
1607 pub mod RW {}
1608 }
1609
1610 /// Operation error
1611 pub mod OPERR {
1612 /// Offset (1 bits)
1613 pub const offset: u32 = 1;
1614 /// Mask (1 bit: 1 << 1)
1615 pub const mask: u32 = 1 << offset;
1616 /// Read-only values
1617 pub mod R {
1618
1619 /// 0b0: No memory opreation error happened
1620 pub const NoError: u32 = 0b0;
1621
1622 /// 0b1: Memory operation error happened
1623 pub const Error: u32 = 0b1;
1624 }
1625 pub use super::EOP::W;
1626 /// Read-write values (empty)
1627 pub mod RW {}
1628 }
1629
1630 /// Programming error
1631 pub mod PROGERR {
1632 /// Offset (3 bits)
1633 pub const offset: u32 = 3;
1634 /// Mask (1 bit: 1 << 3)
1635 pub const mask: u32 = 1 << offset;
1636 /// Read-only values
1637 pub mod R {
1638
1639 /// 0b0: No size programming error happened
1640 pub const NoError: u32 = 0b0;
1641
1642 /// 0b1: Programming error happened
1643 pub const Error: u32 = 0b1;
1644 }
1645 pub use super::EOP::W;
1646 /// Read-write values (empty)
1647 pub mod RW {}
1648 }
1649
1650 /// WRPERR
1651 pub mod WRPERR {
1652 /// Offset (4 bits)
1653 pub const offset: u32 = 4;
1654 /// Mask (1 bit: 1 << 4)
1655 pub const mask: u32 = 1 << offset;
1656 /// Read-only values
1657 pub mod R {
1658
1659 /// 0b0: No write protection error happened
1660 pub const NoError: u32 = 0b0;
1661
1662 /// 0b1: Write protection error happened
1663 pub const Error: u32 = 0b1;
1664 }
1665 pub use super::EOP::W;
1666 /// Read-write values (empty)
1667 pub mod RW {}
1668 }
1669
1670 /// PGAERR
1671 pub mod PGAERR {
1672 /// Offset (5 bits)
1673 pub const offset: u32 = 5;
1674 /// Mask (1 bit: 1 << 5)
1675 pub const mask: u32 = 1 << offset;
1676 /// Read-only values
1677 pub mod R {
1678
1679 /// 0b0: No programming alignment error happened
1680 pub const NoError: u32 = 0b0;
1681
1682 /// 0b1: Programming alignment error happened
1683 pub const Error: u32 = 0b1;
1684 }
1685 pub use super::EOP::W;
1686 /// Read-write values (empty)
1687 pub mod RW {}
1688 }
1689
1690 /// Size error
1691 pub mod SIZERR {
1692 /// Offset (6 bits)
1693 pub const offset: u32 = 6;
1694 /// Mask (1 bit: 1 << 6)
1695 pub const mask: u32 = 1 << offset;
1696 /// Read-only values
1697 pub mod R {
1698
1699 /// 0b0: No size error happened
1700 pub const NoError: u32 = 0b0;
1701
1702 /// 0b1: Size error happened
1703 pub const Error: u32 = 0b1;
1704 }
1705 pub use super::EOP::W;
1706 /// Read-write values (empty)
1707 pub mod RW {}
1708 }
1709
1710 /// Programming sequence error
1711 pub mod PGSERR {
1712 /// Offset (7 bits)
1713 pub const offset: u32 = 7;
1714 /// Mask (1 bit: 1 << 7)
1715 pub const mask: u32 = 1 << offset;
1716 /// Read-only values
1717 pub mod R {
1718
1719 /// 0b0: No fast programming sequence error happened
1720 pub const NoError: u32 = 0b0;
1721
1722 /// 0b1: Fast programming sequence error happened
1723 pub const Error: u32 = 0b1;
1724 }
1725 pub use super::EOP::W;
1726 /// Read-write values (empty)
1727 pub mod RW {}
1728 }
1729
1730 /// Fast programming data miss error
1731 pub mod MISSERR {
1732 /// Offset (8 bits)
1733 pub const offset: u32 = 8;
1734 /// Mask (1 bit: 1 << 8)
1735 pub const mask: u32 = 1 << offset;
1736 /// Read-only values
1737 pub mod R {
1738
1739 /// 0b0: No fast programming data miss error happened
1740 pub const NoError: u32 = 0b0;
1741
1742 /// 0b1: Fast programming data miss error happened
1743 pub const Error: u32 = 0b1;
1744 }
1745 pub use super::EOP::W;
1746 /// Read-write values (empty)
1747 pub mod RW {}
1748 }
1749
1750 /// Fast programming error
1751 pub mod FASTERR {
1752 /// Offset (9 bits)
1753 pub const offset: u32 = 9;
1754 /// Mask (1 bit: 1 << 9)
1755 pub const mask: u32 = 1 << offset;
1756 /// Read-only values
1757 pub mod R {
1758
1759 /// 0b0: No fast programming error happened
1760 pub const NoError: u32 = 0b0;
1761
1762 /// 0b1: Fast programming error happened
1763 pub const Error: u32 = 0b1;
1764 }
1765 pub use super::EOP::W;
1766 /// Read-write values (empty)
1767 pub mod RW {}
1768 }
1769
1770 /// PCROP read error
1771 pub mod RDERR {
1772 /// Offset (14 bits)
1773 pub const offset: u32 = 14;
1774 /// Mask (1 bit: 1 << 14)
1775 pub const mask: u32 = 1 << offset;
1776 /// Read-only values
1777 pub mod R {
1778
1779 /// 0b0: No read-only error happened
1780 pub const NoError: u32 = 0b0;
1781
1782 /// 0b1: Read-only error happened
1783 pub const Error: u32 = 0b1;
1784 }
1785 pub use super::EOP::W;
1786 /// Read-write values (empty)
1787 pub mod RW {}
1788 }
1789
1790 /// BSY
1791 pub mod BSY {
1792 /// Offset (16 bits)
1793 pub const offset: u32 = 16;
1794 /// Mask (1 bit: 1 << 16)
1795 pub const mask: u32 = 1 << offset;
1796 /// Read-only values
1797 pub mod R {
1798
1799 /// 0b0: No write/erase operation is in progress
1800 pub const Inactive: u32 = 0b0;
1801
1802 /// 0b1: No write/erase operation is in progress
1803 pub const Active: u32 = 0b1;
1804 }
1805 /// Write-only values (empty)
1806 pub mod W {}
1807 /// Read-write values (empty)
1808 pub mod RW {}
1809 }
1810
1811 /// CFGBSY
1812 pub mod CFGBSY {
1813 /// Offset (18 bits)
1814 pub const offset: u32 = 18;
1815 /// Mask (1 bit: 1 << 18)
1816 pub const mask: u32 = 1 << offset;
1817 /// Read-only values
1818 pub mod R {
1819
1820 /// 0b0: PG, PNB, PER, MER bits available for writing
1821 pub const Free: u32 = 0b0;
1822
1823 /// 0b1: PG, PNB, PER, MER bits not available for writing (operation ongoing)
1824 pub const Busy: u32 = 0b1;
1825 }
1826 /// Write-only values (empty)
1827 pub mod W {}
1828 /// Read-write values (empty)
1829 pub mod RW {}
1830 }
1831
1832 /// PESD
1833 pub mod PESD {
1834 /// Offset (19 bits)
1835 pub const offset: u32 = 19;
1836 /// Mask (1 bit: 1 << 19)
1837 pub const mask: u32 = 1 << offset;
1838 /// Read-only values
1839 pub mod R {
1840
1841 /// 0b0: Flash program and erase operations granted
1842 pub const Granted: u32 = 0b0;
1843
1844 /// 0b1: Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set.
1845 pub const Suspended: u32 = 0b1;
1846 }
1847 /// Write-only values (empty)
1848 pub mod W {}
1849 /// Read-write values (empty)
1850 pub mod RW {}
1851 }
1852}
1853
1854/// Flash CPU2 control register
1855pub mod C2CR {
1856
1857 /// Programming
1858 pub mod PG {
1859 /// Offset (0 bits)
1860 pub const offset: u32 = 0;
1861 /// Mask (1 bit: 1 << 0)
1862 pub const mask: u32 = 1 << offset;
1863 /// Read-only values (empty)
1864 pub mod R {}
1865 /// Write-only values (empty)
1866 pub mod W {}
1867 /// Read-write values
1868 pub mod RW {
1869
1870 /// 0b0: Flash programming disabled
1871 pub const Disabled: u32 = 0b0;
1872
1873 /// 0b1: Flash programming enabled
1874 pub const Enabled: u32 = 0b1;
1875 }
1876 }
1877
1878 /// Page erase
1879 pub mod PER {
1880 /// Offset (1 bits)
1881 pub const offset: u32 = 1;
1882 /// Mask (1 bit: 1 << 1)
1883 pub const mask: u32 = 1 << offset;
1884 /// Read-only values (empty)
1885 pub mod R {}
1886 /// Write-only values (empty)
1887 pub mod W {}
1888 /// Read-write values
1889 pub mod RW {
1890
1891 /// 0b0: Page erase disabled
1892 pub const Disabled: u32 = 0b0;
1893
1894 /// 0b1: Page erase enabled
1895 pub const Enabled: u32 = 0b1;
1896 }
1897 }
1898
1899 /// Mass erase
1900 pub mod MER {
1901 /// Offset (2 bits)
1902 pub const offset: u32 = 2;
1903 /// Mask (1 bit: 1 << 2)
1904 pub const mask: u32 = 1 << offset;
1905 /// Read-only values (empty)
1906 pub mod R {}
1907 /// Write-only values (empty)
1908 pub mod W {}
1909 /// Read-write values
1910 pub mod RW {
1911
1912 /// 0b0: No mass erase
1913 pub const NoErase: u32 = 0b0;
1914
1915 /// 0b1: Trigger mass erase
1916 pub const MassErase: u32 = 0b1;
1917 }
1918 }
1919
1920 /// Page number selection
1921 pub mod PNB {
1922 /// Offset (3 bits)
1923 pub const offset: u32 = 3;
1924 /// Mask (7 bits: 0x7f << 3)
1925 pub const mask: u32 = 0x7f << offset;
1926 /// Read-only values (empty)
1927 pub mod R {}
1928 /// Write-only values (empty)
1929 pub mod W {}
1930 /// Read-write values (empty)
1931 pub mod RW {}
1932 }
1933
1934 /// Start
1935 pub mod STRT {
1936 /// Offset (16 bits)
1937 pub const offset: u32 = 16;
1938 /// Mask (1 bit: 1 << 16)
1939 pub const mask: u32 = 1 << offset;
1940 /// Read-only values
1941 pub mod R {
1942
1943 /// 0b0: Options modification completed or idle
1944 pub const Done: u32 = 0b0;
1945 }
1946 /// Write-only values
1947 pub mod W {
1948
1949 /// 0b1: Trigger options programming operation
1950 pub const Start: u32 = 0b1;
1951 }
1952 /// Read-write values (empty)
1953 pub mod RW {}
1954 }
1955
1956 /// Fast programming
1957 pub mod FSTPG {
1958 /// Offset (18 bits)
1959 pub const offset: u32 = 18;
1960 /// Mask (1 bit: 1 << 18)
1961 pub const mask: u32 = 1 << offset;
1962 /// Read-only values (empty)
1963 pub mod R {}
1964 /// Write-only values (empty)
1965 pub mod W {}
1966 /// Read-write values
1967 pub mod RW {
1968
1969 /// 0b0: Fast programming disabled
1970 pub const Disabled: u32 = 0b0;
1971
1972 /// 0b1: Fast programming enabled
1973 pub const Enabled: u32 = 0b1;
1974 }
1975 }
1976
1977 /// End of operation interrupt enable
1978 pub mod EOPIE {
1979 /// Offset (24 bits)
1980 pub const offset: u32 = 24;
1981 /// Mask (1 bit: 1 << 24)
1982 pub const mask: u32 = 1 << offset;
1983 /// Read-only values (empty)
1984 pub mod R {}
1985 /// Write-only values (empty)
1986 pub mod W {}
1987 /// Read-write values
1988 pub mod RW {
1989
1990 /// 0b0: End of program interrupt disable
1991 pub const Disabled: u32 = 0b0;
1992
1993 /// 0b1: End of program interrupt enable
1994 pub const Enabled: u32 = 0b1;
1995 }
1996 }
1997
1998 /// Error interrupt enable
1999 pub mod ERRIE {
2000 /// Offset (25 bits)
2001 pub const offset: u32 = 25;
2002 /// Mask (1 bit: 1 << 25)
2003 pub const mask: u32 = 1 << offset;
2004 /// Read-only values (empty)
2005 pub mod R {}
2006 /// Write-only values (empty)
2007 pub mod W {}
2008 /// Read-write values
2009 pub mod RW {
2010
2011 /// 0b0: OPERR Error interrupt disable
2012 pub const Disabled: u32 = 0b0;
2013
2014 /// 0b1: OPERR Error interrupt enable
2015 pub const Enabled: u32 = 0b1;
2016 }
2017 }
2018
2019 /// RDERRIE
2020 pub mod RDERRIE {
2021 /// Offset (26 bits)
2022 pub const offset: u32 = 26;
2023 /// Mask (1 bit: 1 << 26)
2024 pub const mask: u32 = 1 << offset;
2025 /// Read-only values (empty)
2026 pub mod R {}
2027 /// Write-only values (empty)
2028 pub mod W {}
2029 /// Read-write values
2030 pub mod RW {
2031
2032 /// 0b0: PCROP read error interrupt disable
2033 pub const Disabled: u32 = 0b0;
2034
2035 /// 0b1: PCROP read error interrupt enable
2036 pub const Enabled: u32 = 0b1;
2037 }
2038 }
2039}
2040
2041/// Flash secure Flash start address register
2042pub mod SFR {
2043
2044 /// Secure Flash start address
2045 pub mod SFSA {
2046 /// Offset (0 bits)
2047 pub const offset: u32 = 0;
2048 /// Mask (7 bits: 0x7f << 0)
2049 pub const mask: u32 = 0x7f << offset;
2050 /// Read-only values (empty)
2051 pub mod R {}
2052 /// Write-only values (empty)
2053 pub mod W {}
2054 /// Read-write values (empty)
2055 pub mod RW {}
2056 }
2057
2058 /// Flash security disabled
2059 pub mod FSD {
2060 /// Offset (7 bits)
2061 pub const offset: u32 = 7;
2062 /// Mask (1 bit: 1 << 7)
2063 pub const mask: u32 = 1 << offset;
2064 /// Read-only values (empty)
2065 pub mod R {}
2066 /// Write-only values (empty)
2067 pub mod W {}
2068 /// Read-write values
2069 pub mod RW {
2070
2071 /// 0b0: System and Flash memory secure
2072 pub const Secure: u32 = 0b0;
2073
2074 /// 0b1: System and Flash memory non-secure
2075 pub const NonSecure: u32 = 0b1;
2076 }
2077 }
2078
2079 /// DDS
2080 pub mod DDS {
2081 /// Offset (12 bits)
2082 pub const offset: u32 = 12;
2083 /// Mask (1 bit: 1 << 12)
2084 pub const mask: u32 = 1 << offset;
2085 /// Read-only values (empty)
2086 pub mod R {}
2087 /// Write-only values (empty)
2088 pub mod W {}
2089 /// Read-write values
2090 pub mod RW {
2091
2092 /// 0b0: CPU2 debug access enabled
2093 pub const Enabled: u32 = 0b0;
2094
2095 /// 0b1: CPU2 debug access disabled
2096 pub const Disabled: u32 = 0b1;
2097 }
2098 }
2099
2100 /// User Flash hide protection area start address
2101 pub mod HDPSA {
2102 /// Offset (16 bits)
2103 pub const offset: u32 = 16;
2104 /// Mask (7 bits: 0x7f << 16)
2105 pub const mask: u32 = 0x7f << offset;
2106 /// Read-only values (empty)
2107 pub mod R {}
2108 /// Write-only values (empty)
2109 pub mod W {}
2110 /// Read-write values (empty)
2111 pub mod RW {}
2112 }
2113
2114 /// User Flash hide protection area disabled
2115 pub mod HDPAD {
2116 /// Offset (23 bits)
2117 pub const offset: u32 = 23;
2118 /// Mask (1 bit: 1 << 23)
2119 pub const mask: u32 = 1 << offset;
2120 /// Read-only values (empty)
2121 pub mod R {}
2122 /// Write-only values (empty)
2123 pub mod W {}
2124 /// Read-write values
2125 pub mod RW {
2126
2127 /// 0b0: User Flash memory hide protection area enabled. HDPSA\[6:0\] contains the start address of the first 2-Kbyte page of the user Flash memory hide protection area
2128 pub const Enabled: u32 = 0b0;
2129
2130 /// 0b1: User Flash memory hide protection area disabled
2131 pub const Disabled: u32 = 0b1;
2132 }
2133 }
2134
2135 /// sub-GHz radio SPI security disable
2136 pub mod SUBGHSPISD {
2137 /// Offset (31 bits)
2138 pub const offset: u32 = 31;
2139 /// Mask (1 bit: 1 << 31)
2140 pub const mask: u32 = 1 << offset;
2141 /// Read-only values (empty)
2142 pub mod R {}
2143 /// Write-only values (empty)
2144 pub mod W {}
2145 /// Read-write values
2146 pub mod RW {
2147
2148 /// 0b0: sub-GHz radio SPI security enabled
2149 pub const Enabled: u32 = 0b0;
2150
2151 /// 0b1: sub-GHz radio SPI security disabled
2152 pub const Disabled: u32 = 0b1;
2153 }
2154 }
2155}
2156
2157/// Flash secure SRAM start address and CPU2 reset vector register
2158pub mod SRRVR {
2159
2160 /// CPU2 boot reset vector
2161 pub mod SBRV {
2162 /// Offset (0 bits)
2163 pub const offset: u32 = 0;
2164 /// Mask (16 bits: 0xffff << 0)
2165 pub const mask: u32 = 0xffff << offset;
2166 /// Read-only values (empty)
2167 pub mod R {}
2168 /// Write-only values (empty)
2169 pub mod W {}
2170 /// Read-write values (empty)
2171 pub mod RW {}
2172 }
2173
2174 /// Secure backup SRAM2 start address
2175 pub mod SBRSA {
2176 /// Offset (18 bits)
2177 pub const offset: u32 = 18;
2178 /// Mask (5 bits: 0b11111 << 18)
2179 pub const mask: u32 = 0b11111 << offset;
2180 /// Read-only values (empty)
2181 pub mod R {}
2182 /// Write-only values (empty)
2183 pub mod W {}
2184 /// Read-write values (empty)
2185 pub mod RW {}
2186 }
2187
2188 /// backup SRAM2 security disable
2189 pub mod BRSD {
2190 /// Offset (23 bits)
2191 pub const offset: u32 = 23;
2192 /// Mask (1 bit: 1 << 23)
2193 pub const mask: u32 = 1 << offset;
2194 /// Read-only values (empty)
2195 pub mod R {}
2196 /// Write-only values (empty)
2197 pub mod W {}
2198 /// Read-write values
2199 pub mod RW {
2200
2201 /// 0b0: SRAM2 is secure. SNBRSA\[4:0\] contains the start address of the first 1-Kbyte page of the secure backup SRAM2 area
2202 pub const Secure: u32 = 0b0;
2203
2204 /// 0b1: SRAM2 is non-secure
2205 pub const NonSecure: u32 = 0b1;
2206 }
2207 }
2208
2209 /// Secure non-backup SRAM1 start address
2210 pub mod SNBRSA {
2211 /// Offset (25 bits)
2212 pub const offset: u32 = 25;
2213 /// Mask (5 bits: 0b11111 << 25)
2214 pub const mask: u32 = 0b11111 << offset;
2215 /// Read-only values (empty)
2216 pub mod R {}
2217 /// Write-only values (empty)
2218 pub mod W {}
2219 /// Read-write values (empty)
2220 pub mod RW {}
2221 }
2222
2223 /// NBRSD
2224 pub mod NBRSD {
2225 /// Offset (30 bits)
2226 pub const offset: u32 = 30;
2227 /// Mask (1 bit: 1 << 30)
2228 pub const mask: u32 = 1 << offset;
2229 /// Read-only values (empty)
2230 pub mod R {}
2231 /// Write-only values (empty)
2232 pub mod W {}
2233 /// Read-write values
2234 pub mod RW {
2235
2236 /// 0b0: SRAM1 is secure. SNBRSA\[4:0\] contains the start address of the first 1-Kbyte page of the secure non-backup SRAM1 area
2237 pub const Secure: u32 = 0b0;
2238
2239 /// 0b1: SRAM1 is non-secure
2240 pub const NonSecure: u32 = 0b1;
2241 }
2242 }
2243
2244 /// C2OPT
2245 pub mod C2OPT {
2246 /// Offset (31 bits)
2247 pub const offset: u32 = 31;
2248 /// Mask (1 bit: 1 << 31)
2249 pub const mask: u32 = 1 << offset;
2250 /// Read-only values (empty)
2251 pub mod R {}
2252 /// Write-only values (empty)
2253 pub mod W {}
2254 /// Read-write values
2255 pub mod RW {
2256
2257 /// 0b0: SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000_0000 + SBRV
2258 pub const SRAM: u32 = 0b0;
2259
2260 /// 0b1: SBRV offset addresses the Flash memory, from start address 0x0800_0000 + SBRV
2261 pub const Flash: u32 = 0b1;
2262 }
2263 }
2264}
2265#[repr(C)]
2266pub struct RegisterBlock {
2267 /// Access control register
2268 pub ACR: RWRegister<u32>,
2269
2270 /// Flash access control register 2
2271 pub ACR2: RWRegister<u32>,
2272
2273 /// Flash key register
2274 pub KEYR: WORegister<u32>,
2275
2276 /// Option byte key register
2277 pub OPTKEYR: WORegister<u32>,
2278
2279 /// Status register
2280 pub SR: RWRegister<u32>,
2281
2282 /// Flash control register
2283 pub CR: RWRegister<u32>,
2284
2285 /// Flash ECC register
2286 pub ECCR: RWRegister<u32>,
2287
2288 _reserved1: [u8; 4],
2289
2290 /// Flash option register
2291 pub OPTR: RWRegister<u32>,
2292
2293 /// Flash PCROP zone A Start address register
2294 pub PCROP1ASR: RWRegister<u32>,
2295
2296 /// Flash PCROP zone A End address register
2297 pub PCROP1AER: RWRegister<u32>,
2298
2299 /// Flash WRP area A address register
2300 pub WRP1AR: RWRegister<u32>,
2301
2302 /// Flash WRP area B address register
2303 pub WRP1BR: RWRegister<u32>,
2304
2305 /// Flash PCROP zone B Start address register
2306 pub PCROP1BSR: RWRegister<u32>,
2307
2308 /// Flash PCROP zone B End address register
2309 pub PCROP1BER: RWRegister<u32>,
2310
2311 /// Flash IPCC data buffer address register
2312 pub IPCCBR: RWRegister<u32>,
2313
2314 _reserved2: [u8; 28],
2315
2316 /// Flash CPU2 access control register
2317 pub C2ACR: RWRegister<u32>,
2318
2319 /// Flash CPU2 status register
2320 pub C2SR: RWRegister<u32>,
2321
2322 /// Flash CPU2 control register
2323 pub C2CR: RWRegister<u32>,
2324
2325 _reserved3: [u8; 24],
2326
2327 /// Flash secure Flash start address register
2328 pub SFR: RWRegister<u32>,
2329
2330 /// Flash secure SRAM start address and CPU2 reset vector register
2331 pub SRRVR: RWRegister<u32>,
2332}
2333pub struct ResetValues {
2334 pub ACR: u32,
2335 pub ACR2: u32,
2336 pub KEYR: u32,
2337 pub OPTKEYR: u32,
2338 pub SR: u32,
2339 pub CR: u32,
2340 pub ECCR: u32,
2341 pub OPTR: u32,
2342 pub PCROP1ASR: u32,
2343 pub PCROP1AER: u32,
2344 pub WRP1AR: u32,
2345 pub WRP1BR: u32,
2346 pub PCROP1BSR: u32,
2347 pub PCROP1BER: u32,
2348 pub IPCCBR: u32,
2349 pub C2ACR: u32,
2350 pub C2SR: u32,
2351 pub C2CR: u32,
2352 pub SFR: u32,
2353 pub SRRVR: u32,
2354}
2355#[cfg(not(feature = "nosync"))]
2356pub struct Instance {
2357 pub(crate) addr: u32,
2358 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2359}
2360#[cfg(not(feature = "nosync"))]
2361impl ::core::ops::Deref for Instance {
2362 type Target = RegisterBlock;
2363 #[inline(always)]
2364 fn deref(&self) -> &RegisterBlock {
2365 unsafe { &*(self.addr as *const _) }
2366 }
2367}
2368#[cfg(feature = "rtic")]
2369unsafe impl Send for Instance {}