Constant stm32ral::stm32g0::stm32g0c1::rng::RNG_SR::CECS::RW::B_0x0

pub const B_0x0: u32 = 0b0;

0b0: The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.