Module stm32mp1::stm32mp157::tim1
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TIM1
Modules
TIM1 alternate function option register 1
TIM1 Alternate function register 2
TIM1 auto-reload register
As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
TIM1 capture/compare enable register
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The channels 5 and 6 can only be configured in output. Output compare mode:
TIM1 capture/compare register 1
TIM1 capture/compare register 2
TIM1 capture/compare register 3
TIM1 capture/compare register 4
TIM1 capture/compare register 5
TIM1 capture/compare register 6
TIM1 counter
TIM1 control register 1
TIM1 control register 2
TIM1 DMA control register
TIM1 DMA/interrupt enable register
TIM1 DMA address for full transfer
TIM1 event generation register
TIM1 prescaler
TIM1 repetition counter register
TIM1 slave mode control register
TIM1 status register
TIM1 timer input selection register
Structs
Register block
Type Definitions
TIM1_AF1 register accessor: an alias for Reg<TIM1_AF1_SPEC>
TIM1_AF2 register accessor: an alias for Reg<TIM1_AF2_SPEC>
TIM1_ARR register accessor: an alias for Reg<TIM1_ARR_SPEC>
TIM1_BDTR register accessor: an alias for Reg<TIM1_BDTR_SPEC>
TIM1_CCER register accessor: an alias for Reg<TIM1_CCER_SPEC>
TIM1_CCMR1ALTERNATE1 register accessor: an alias for Reg<TIM1_CCMR1ALTERNATE1_SPEC>
TIM1_CCMR2ALTERNATE17 register accessor: an alias for Reg<TIM1_CCMR2ALTERNATE17_SPEC>
TIM1_CCMR3 register accessor: an alias for Reg<TIM1_CCMR3_SPEC>
TIM1_CCR1 register accessor: an alias for Reg<TIM1_CCR1_SPEC>
TIM1_CCR2 register accessor: an alias for Reg<TIM1_CCR2_SPEC>
TIM1_CCR3 register accessor: an alias for Reg<TIM1_CCR3_SPEC>
TIM1_CCR4 register accessor: an alias for Reg<TIM1_CCR4_SPEC>
TIM1_CCR5 register accessor: an alias for Reg<TIM1_CCR5_SPEC>
TIM1_CCR6 register accessor: an alias for Reg<TIM1_CCR6_SPEC>
TIM1_CNT register accessor: an alias for Reg<TIM1_CNT_SPEC>
TIM1_CR1 register accessor: an alias for Reg<TIM1_CR1_SPEC>
TIM1_CR2 register accessor: an alias for Reg<TIM1_CR2_SPEC>
TIM1_DCR register accessor: an alias for Reg<TIM1_DCR_SPEC>
TIM1_DIER register accessor: an alias for Reg<TIM1_DIER_SPEC>
TIM1_DMAR register accessor: an alias for Reg<TIM1_DMAR_SPEC>
TIM1_EGR register accessor: an alias for Reg<TIM1_EGR_SPEC>
TIM1_PSC register accessor: an alias for Reg<TIM1_PSC_SPEC>
TIM1_RCR register accessor: an alias for Reg<TIM1_RCR_SPEC>
TIM1_SMCR register accessor: an alias for Reg<TIM1_SMCR_SPEC>
TIM1_SR register accessor: an alias for Reg<TIM1_SR_SPEC>
TIM1_TISEL register accessor: an alias for Reg<TIM1_TISEL_SPEC>