Module stm32mp1::stm32mp157::ltdc
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LTDC
Modules
This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
This register defines the background color (RGB888).
This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.
LTDC current position status register
LTDC global configuration 1 register
LTDC global configuration 2 register
This register defines the global configuration of the LCD-TFT controller.
LTDC Interrupt Clear Register
LTDC identification register
This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
This register returns the interrupt status flag.
This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
This register defines the number of lines in the color frame buffer.
This register defines the color frame buffer line length and pitch.
This register defines the color key value (RGB), that is used by the color keying.
This register defines the CLUT address and the RGB value.
LTDC layer 1 control register
This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
This register defines the number of lines in the color frame buffer.
This register defines the color frame buffer line length and pitch.
This register defines the color key value (RGB), that is used by the color keying.
This register defines the CLUT address and the RGB value.
LTDC layer 2 control register
This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
LDTC layer count register
This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274.
This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
Structs
Register block
Type Definitions
LTDC_AWCR register accessor: an alias for Reg<LTDC_AWCR_SPEC>
LTDC_BCCR register accessor: an alias for Reg<LTDC_BCCR_SPEC>
LTDC_BPCR register accessor: an alias for Reg<LTDC_BPCR_SPEC>
LTDC_CDSR register accessor: an alias for Reg<LTDC_CDSR_SPEC>
LTDC_CPSR register accessor: an alias for Reg<LTDC_CPSR_SPEC>
LTDC_GC1R register accessor: an alias for Reg<LTDC_GC1R_SPEC>
LTDC_GC2R register accessor: an alias for Reg<LTDC_GC2R_SPEC>
LTDC_GCR register accessor: an alias for Reg<LTDC_GCR_SPEC>
LTDC_ICR register accessor: an alias for Reg<LTDC_ICR_SPEC>
LTDC_IDR register accessor: an alias for Reg<LTDC_IDR_SPEC>
LTDC_IER register accessor: an alias for Reg<LTDC_IER_SPEC>
LTDC_ISR register accessor: an alias for Reg<LTDC_ISR_SPEC>
LTDC_L1BFCR register accessor: an alias for Reg<LTDC_L1BFCR_SPEC>
LTDC_L1CACR register accessor: an alias for Reg<LTDC_L1CACR_SPEC>
LTDC_L1CFBAR register accessor: an alias for Reg<LTDC_L1CFBAR_SPEC>
LTDC_L1CFBLNR register accessor: an alias for Reg<LTDC_L1CFBLNR_SPEC>
LTDC_L1CFBLR register accessor: an alias for Reg<LTDC_L1CFBLR_SPEC>
LTDC_L1CKCR register accessor: an alias for Reg<LTDC_L1CKCR_SPEC>
LTDC_L1CLUTWR register accessor: an alias for Reg<LTDC_L1CLUTWR_SPEC>
LTDC_L1CR register accessor: an alias for Reg<LTDC_L1CR_SPEC>
LTDC_L1DCCR register accessor: an alias for Reg<LTDC_L1DCCR_SPEC>
LTDC_L1PFCR register accessor: an alias for Reg<LTDC_L1PFCR_SPEC>
LTDC_L1WHPCR register accessor: an alias for Reg<LTDC_L1WHPCR_SPEC>
LTDC_L1WVPCR register accessor: an alias for Reg<LTDC_L1WVPCR_SPEC>
LTDC_L2BFCR register accessor: an alias for Reg<LTDC_L2BFCR_SPEC>
LTDC_L2CACR register accessor: an alias for Reg<LTDC_L2CACR_SPEC>
LTDC_L2CFBAR register accessor: an alias for Reg<LTDC_L2CFBAR_SPEC>
LTDC_L2CFBLNR register accessor: an alias for Reg<LTDC_L2CFBLNR_SPEC>
LTDC_L2CFBLR register accessor: an alias for Reg<LTDC_L2CFBLR_SPEC>
LTDC_L2CKCR register accessor: an alias for Reg<LTDC_L2CKCR_SPEC>
LTDC_L2CLUTWR register accessor: an alias for Reg<LTDC_L2CLUTWR_SPEC>
LTDC_L2CR register accessor: an alias for Reg<LTDC_L2CR_SPEC>
LTDC_L2DCCR register accessor: an alias for Reg<LTDC_L2DCCR_SPEC>
LTDC_L2PFCR register accessor: an alias for Reg<LTDC_L2PFCR_SPEC>
LTDC_L2WHPCR register accessor: an alias for Reg<LTDC_L2WHPCR_SPEC>
LTDC_L2WVPCR register accessor: an alias for Reg<LTDC_L2WVPCR_SPEC>
LTDC_LCR register accessor: an alias for Reg<LTDC_LCR_SPEC>
LTDC_LIPCR register accessor: an alias for Reg<LTDC_LIPCR_SPEC>
LTDC_SRCR register accessor: an alias for Reg<LTDC_SRCR_SPEC>
LTDC_SSCR register accessor: an alias for Reg<LTDC_SSCR_SPEC>
LTDC_TWCR register accessor: an alias for Reg<LTDC_TWCR_SPEC>