Module stm32mp1::stm32mp157::gicd::gicd_itargetsr20

source · [−]
Expand description

GICD interrupt processor target register 20

Structs

GICD_ITARGETSR20_SPEC

GICD interrupt processor target register 20

R

Register GICD_ITARGETSR20 reader

W

Register GICD_ITARGETSR20 writer

Type Definitions

CPU_TARGETS0_R

Field CPU_TARGETS0 reader - CPU_TARGETS0

CPU_TARGETS0_W

Field CPU_TARGETS0 writer - CPU_TARGETS0

CPU_TARGETS1_R

Field CPU_TARGETS1 reader - CPU_TARGETS1

CPU_TARGETS1_W

Field CPU_TARGETS1 writer - CPU_TARGETS1

CPU_TARGETS2_R

Field CPU_TARGETS2 reader - CPU_TARGETS2

CPU_TARGETS2_W

Field CPU_TARGETS2 writer - CPU_TARGETS2

CPU_TARGETS3_R

Field CPU_TARGETS3 reader - CPU_TARGETS3

CPU_TARGETS3_W

Field CPU_TARGETS3 writer - CPU_TARGETS3