Expand description

This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.

Structs

This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.

Register FMC_CSQAR1 reader

Register FMC_CSQAR1 writer

Type Definitions

Field ADDC1 reader - ADDC1

Field ADDC1 writer - ADDC1

Field ADDC2 reader - ADDC2

Field ADDC2 writer - ADDC2

Field ADDC3 reader - ADDC3

Field ADDC3 writer - ADDC3

Field ADDC4 reader - ADDC4

Field ADDC4 writer - ADDC4