Module stm32mp1::stm32mp157::fdcan1
source · [−]Expand description
FDCAN1
Modules
For details about setting and resetting of single bits see Software initialization.
FDCAN core release register
This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
FDCAN error counter register
FDCAN Endian register
Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path.
This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line.
Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.
The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
This register is dedicated to the nominal bit timing used during the arbitration phase.
FDCAN new data 1 register
FDCAN new data 2 register
FDCAN protocol status register
The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock.
FDCAN Rx buffer configuration register
Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only.
FDCAN Rx FIFO 0 acknowledge register
FDCAN Rx FIFO 0 configuration register
FDCAN Rx FIFO 0 status register
FDCAN Rx FIFO 1 acknowledge register
FDCAN Rx FIFO 1 configuration register
FDCAN Rx FIFO 1 status register
Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708.
FDCAN transmitter delay compensation register
Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
FDCAN timeout counter configuration register
FDCAN timeout counter value register
FDCAN timestamp counter configuration register
FDCAN timestamp counter value register
FDCAN TT capture time register
FDCAN TT cycle sync mark register
FDCAN TT cycle time and count register
If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master.
The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt.
The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.
The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
FDCAN TT local and global time register
FDCAN TT matrix limits register
FDCAN TT operation configuration register
FDCAN TT operation control register
FDCAN TT operation status register
FDCAN TT reference message configuration register
FDCAN TT trigger memory configuration register
A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM.
The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger.
The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process.
There is no drift compensation in TTCAN level 1.
FDCAN Tx buffer add request register
FDCAN Tx buffer configuration register
FDCAN Tx buffer cancellation finished register
FDCAN Tx buffer cancellation finished interrupt enable register
FDCAN Tx buffer cancellation request register
FDCAN Tx buffer transmission interrupt enable register
FDCAN Tx buffer transmission occurred register
FDCAN Tx event FIFO acknowledge register
FDCAN Tx event FIFO configuration register
FDCAN Tx event FIFO status register
Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only.
The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated).
FDCAN extended ID and mask register
Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path.
Structs
Register block
Type Definitions
FDCAN_CCCR register accessor: an alias for Reg<FDCAN_CCCR_SPEC>
FDCAN_CREL register accessor: an alias for Reg<FDCAN_CREL_SPEC>
FDCAN_DBTP register accessor: an alias for Reg<FDCAN_DBTP_SPEC>
FDCAN_ECR register accessor: an alias for Reg<FDCAN_ECR_SPEC>
FDCAN_ENDN register accessor: an alias for Reg<FDCAN_ENDN_SPEC>
FDCAN_GFC register accessor: an alias for Reg<FDCAN_GFC_SPEC>
FDCAN_HPMS register accessor: an alias for Reg<FDCAN_HPMS_SPEC>
FDCAN_IE register accessor: an alias for Reg<FDCAN_IE_SPEC>
FDCAN_ILE register accessor: an alias for Reg<FDCAN_ILE_SPEC>
FDCAN_ILS register accessor: an alias for Reg<FDCAN_ILS_SPEC>
FDCAN_IR register accessor: an alias for Reg<FDCAN_IR_SPEC>
FDCAN_NBTP register accessor: an alias for Reg<FDCAN_NBTP_SPEC>
FDCAN_NDAT1 register accessor: an alias for Reg<FDCAN_NDAT1_SPEC>
FDCAN_NDAT2 register accessor: an alias for Reg<FDCAN_NDAT2_SPEC>
FDCAN_PSR register accessor: an alias for Reg<FDCAN_PSR_SPEC>
FDCAN_RWD register accessor: an alias for Reg<FDCAN_RWD_SPEC>
FDCAN_RXBC register accessor: an alias for Reg<FDCAN_RXBC_SPEC>
FDCAN_RXESC register accessor: an alias for Reg<FDCAN_RXESC_SPEC>
FDCAN_RXF0A register accessor: an alias for Reg<FDCAN_RXF0A_SPEC>
FDCAN_RXF0C register accessor: an alias for Reg<FDCAN_RXF0C_SPEC>
FDCAN_RXF0S register accessor: an alias for Reg<FDCAN_RXF0S_SPEC>
FDCAN_RXF1A register accessor: an alias for Reg<FDCAN_RXF1A_SPEC>
FDCAN_RXF1C register accessor: an alias for Reg<FDCAN_RXF1C_SPEC>
FDCAN_RXF1S register accessor: an alias for Reg<FDCAN_RXF1S_SPEC>
FDCAN_SIDFC register accessor: an alias for Reg<FDCAN_SIDFC_SPEC>
FDCAN_TDCR register accessor: an alias for Reg<FDCAN_TDCR_SPEC>
FDCAN_TEST register accessor: an alias for Reg<FDCAN_TEST_SPEC>
FDCAN_TOCC register accessor: an alias for Reg<FDCAN_TOCC_SPEC>
FDCAN_TOCV register accessor: an alias for Reg<FDCAN_TOCV_SPEC>
FDCAN_TSCC register accessor: an alias for Reg<FDCAN_TSCC_SPEC>
FDCAN_TSCV register accessor: an alias for Reg<FDCAN_TSCV_SPEC>
FDCAN_TTCPT register accessor: an alias for Reg<FDCAN_TTCPT_SPEC>
FDCAN_TTCSM register accessor: an alias for Reg<FDCAN_TTCSM_SPEC>
FDCAN_TTCTC register accessor: an alias for Reg<FDCAN_TTCTC_SPEC>
FDCAN_TTGTP register accessor: an alias for Reg<FDCAN_TTGTP_SPEC>
FDCAN_TTIE register accessor: an alias for Reg<FDCAN_TTIE_SPEC>
FDCAN_TTILS register accessor: an alias for Reg<FDCAN_TTILS_SPEC>
FDCAN_TTIR register accessor: an alias for Reg<FDCAN_TTIR_SPEC>
FDCAN_TTLGT register accessor: an alias for Reg<FDCAN_TTLGT_SPEC>
FDCAN_TTMLM register accessor: an alias for Reg<FDCAN_TTMLM_SPEC>
FDCAN_TTOCF register accessor: an alias for Reg<FDCAN_TTOCF_SPEC>
FDCAN_TTOCN register accessor: an alias for Reg<FDCAN_TTOCN_SPEC>
FDCAN_TTOST register accessor: an alias for Reg<FDCAN_TTOST_SPEC>
FDCAN_TTRMC register accessor: an alias for Reg<FDCAN_TTRMC_SPEC>
FDCAN_TTTMC register accessor: an alias for Reg<FDCAN_TTTMC_SPEC>
FDCAN_TTTMK register accessor: an alias for Reg<FDCAN_TTTMK_SPEC>
FDCAN_TTTS register accessor: an alias for Reg<FDCAN_TTTS_SPEC>
FDCAN_TURCF register accessor: an alias for Reg<FDCAN_TURCF_SPEC>
FDCAN_TURNA register accessor: an alias for Reg<FDCAN_TURNA_SPEC>
FDCAN_TXBAR register accessor: an alias for Reg<FDCAN_TXBAR_SPEC>
FDCAN_TXBC register accessor: an alias for Reg<FDCAN_TXBC_SPEC>
FDCAN_TXBCF register accessor: an alias for Reg<FDCAN_TXBCF_SPEC>
FDCAN_TXBCIE register accessor: an alias for Reg<FDCAN_TXBCIE_SPEC>
FDCAN_TXBCR register accessor: an alias for Reg<FDCAN_TXBCR_SPEC>
FDCAN_TXBTIE register accessor: an alias for Reg<FDCAN_TXBTIE_SPEC>
FDCAN_TXBTO register accessor: an alias for Reg<FDCAN_TXBTO_SPEC>
FDCAN_TXEFA register accessor: an alias for Reg<FDCAN_TXEFA_SPEC>
FDCAN_TXEFC register accessor: an alias for Reg<FDCAN_TXEFC_SPEC>
FDCAN_TXEFS register accessor: an alias for Reg<FDCAN_TXEFS_SPEC>
FDCAN_TXESC register accessor: an alias for Reg<FDCAN_TXESC_SPEC>
FDCAN_TXFQS register accessor: an alias for Reg<FDCAN_TXFQS_SPEC>
FDCAN_XIDAM register accessor: an alias for Reg<FDCAN_XIDAM_SPEC>
FDCAN_XIDFC register accessor: an alias for Reg<FDCAN_XIDFC_SPEC>