Module stm32mp1::stm32mp157::cryp1
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CRYP1
Modules
CRYP control register
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.
CRYP DMA control register
The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.
CRYP hardware configuration register
The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.
CRYP Identification
The CRYP_IV0…1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).
Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2…K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
CRYP HW Magic ID
The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.
The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.
CRYP status register
CRYP HW Version Register
Structs
Register block
Type Definitions
CRYP_CR register accessor: an alias for Reg<CRYP_CR_SPEC>
CRYP_CSGCM0R register accessor: an alias for Reg<CRYP_CSGCM0R_SPEC>
CRYP_CSGCM1R register accessor: an alias for Reg<CRYP_CSGCM1R_SPEC>
CRYP_CSGCM2R register accessor: an alias for Reg<CRYP_CSGCM2R_SPEC>
CRYP_CSGCM3R register accessor: an alias for Reg<CRYP_CSGCM3R_SPEC>
CRYP_CSGCM4R register accessor: an alias for Reg<CRYP_CSGCM4R_SPEC>
CRYP_CSGCM5R register accessor: an alias for Reg<CRYP_CSGCM5R_SPEC>
CRYP_CSGCM6R register accessor: an alias for Reg<CRYP_CSGCM6R_SPEC>
CRYP_CSGCM7R register accessor: an alias for Reg<CRYP_CSGCM7R_SPEC>
CRYP_CSGCMCCM0R register accessor: an alias for Reg<CRYP_CSGCMCCM0R_SPEC>
CRYP_CSGCMCCM1R register accessor: an alias for Reg<CRYP_CSGCMCCM1R_SPEC>
CRYP_CSGCMCCM2R register accessor: an alias for Reg<CRYP_CSGCMCCM2R_SPEC>
CRYP_CSGCMCCM3R register accessor: an alias for Reg<CRYP_CSGCMCCM3R_SPEC>
CRYP_CSGCMCCM4R register accessor: an alias for Reg<CRYP_CSGCMCCM4R_SPEC>
CRYP_CSGCMCCM5R register accessor: an alias for Reg<CRYP_CSGCMCCM5R_SPEC>
CRYP_CSGCMCCM6R register accessor: an alias for Reg<CRYP_CSGCMCCM6R_SPEC>
CRYP_CSGCMCCM7R register accessor: an alias for Reg<CRYP_CSGCMCCM7R_SPEC>
CRYP_DIN register accessor: an alias for Reg<CRYP_DIN_SPEC>
CRYP_DMACR register accessor: an alias for Reg<CRYP_DMACR_SPEC>
CRYP_DOUT register accessor: an alias for Reg<CRYP_DOUT_SPEC>
CRYP_HWCFGR register accessor: an alias for Reg<CRYP_HWCFGR_SPEC>
CRYP_IMSCR register accessor: an alias for Reg<CRYP_IMSCR_SPEC>
CRYP_IPIDR register accessor: an alias for Reg<CRYP_IPIDR_SPEC>
CRYP_IV0LR register accessor: an alias for Reg<CRYP_IV0LR_SPEC>
CRYP_IV0RR register accessor: an alias for Reg<CRYP_IV0RR_SPEC>
CRYP_IV1LR register accessor: an alias for Reg<CRYP_IV1LR_SPEC>
CRYP_IV1RR register accessor: an alias for Reg<CRYP_IV1RR_SPEC>
CRYP_K0LR register accessor: an alias for Reg<CRYP_K0LR_SPEC>
CRYP_K0RR register accessor: an alias for Reg<CRYP_K0RR_SPEC>
CRYP_K1LR register accessor: an alias for Reg<CRYP_K1LR_SPEC>
CRYP_K1RR register accessor: an alias for Reg<CRYP_K1RR_SPEC>
CRYP_K2LR register accessor: an alias for Reg<CRYP_K2LR_SPEC>
CRYP_K2RR register accessor: an alias for Reg<CRYP_K2RR_SPEC>
CRYP_K3LR register accessor: an alias for Reg<CRYP_K3LR_SPEC>
CRYP_K3RR register accessor: an alias for Reg<CRYP_K3RR_SPEC>
CRYP_MID register accessor: an alias for Reg<CRYP_MID_SPEC>
CRYP_MISR register accessor: an alias for Reg<CRYP_MISR_SPEC>
CRYP_RISR register accessor: an alias for Reg<CRYP_RISR_SPEC>
CRYP_SR register accessor: an alias for Reg<CRYP_SR_SPEC>
CRYP_VERR register accessor: an alias for Reg<CRYP_VERR_SPEC>