[−][src]Module stm32l5::stm32l562::rtc
Real-time clock
Modules
| alrmar | alarm A register |
| alrmassr | alarm A sub second register |
| alrmbr | alarm B register |
| alrmbssr | alarm B sub second register |
| calr | calibration register |
| cr | RTC control register |
| dr | date register |
| icsr | RTC initialization control and status register |
| misr | RTC non-secure masked interrupt status register |
| prer | prescaler register |
| privcr | RTC privilege mode control register |
| scr | RTC status clear register |
| shiftr | shift control register |
| smcr | RTC secure mode control register |
| smisr | RTC secure masked interrupt status register |
| sr | RTC status register |
| ssr | RTC sub second register |
| tr | time register |
| tsdr | time stamp date register |
| tsssr | timestamp sub second register |
| tstr | time stamp time register |
| wpr | write protection register |
| wutr | wakeup timer register |
Structs
| RegisterBlock | Register block |
Type Definitions
| ALRMAR | alarm A register |
| ALRMASSR | alarm A sub second register |
| ALRMBR | alarm B register |
| ALRMBSSR | alarm B sub second register |
| CALR | calibration register |
| CR | RTC control register |
| DR | date register |
| ICSR | RTC initialization control and status register |
| MISR | RTC non-secure masked interrupt status register |
| PRER | prescaler register |
| PRIVCR | RTC privilege mode control register |
| SCR | RTC status clear register |
| SHIFTR | shift control register |
| SMCR | RTC secure mode control register |
| SMISR | RTC secure masked interrupt status register |
| SR | RTC status register |
| SSR | RTC sub second register |
| TR | time register |
| TSDR | time stamp date register |
| TSSSR | timestamp sub second register |
| TSTR | time stamp time register |
| WPR | write protection register |
| WUTR | wakeup timer register |