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#[doc = "Reader of register RNG_CR"] pub type R = crate::R<u32, super::RNG_CR>; #[doc = "Writer for register RNG_CR"] pub type W = crate::W<u32, super::RNG_CR>; #[doc = "Register RNG_CR `reset()`'s with value 0"] impl crate::ResetValue for super::RNG_CR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `RNGEN`"] pub type RNGEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RNGEN`"] pub struct RNGEN_W<'a> { w: &'a mut W, } impl<'a> RNGEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `IE`"] pub type IE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `IE`"] pub struct IE_W<'a> { w: &'a mut W, } impl<'a> IE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `CED`"] pub type CED_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CED`"] pub struct CED_W<'a> { w: &'a mut W, } impl<'a> CED_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = "Reader of field `RNG_CONFIG3`"] pub type RNG_CONFIG3_R = crate::R<u8, u8>; #[doc = "Write proxy for field `RNG_CONFIG3`"] pub struct RNG_CONFIG3_W<'a> { w: &'a mut W, } impl<'a> RNG_CONFIG3_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); self.w } } #[doc = "Reader of field `NISTC`"] pub type NISTC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `NISTC`"] pub struct NISTC_W<'a> { w: &'a mut W, } impl<'a> NISTC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `RNG_CONFIG2`"] pub type RNG_CONFIG2_R = crate::R<u8, u8>; #[doc = "Write proxy for field `RNG_CONFIG2`"] pub struct RNG_CONFIG2_W<'a> { w: &'a mut W, } impl<'a> RNG_CONFIG2_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 13)) | (((value as u32) & 0x07) << 13); self.w } } #[doc = "Reader of field `CLKDIV`"] pub type CLKDIV_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CLKDIV`"] pub struct CLKDIV_W<'a> { w: &'a mut W, } impl<'a> CLKDIV_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); self.w } } #[doc = "Reader of field `RNG_CONFIG1`"] pub type RNG_CONFIG1_R = crate::R<u8, u8>; #[doc = "Write proxy for field `RNG_CONFIG1`"] pub struct RNG_CONFIG1_W<'a> { w: &'a mut W, } impl<'a> RNG_CONFIG1_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3f << 20)) | (((value as u32) & 0x3f) << 20); self.w } } #[doc = "Reader of field `CONDRST`"] pub type CONDRST_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CONDRST`"] pub struct CONDRST_W<'a> { w: &'a mut W, } impl<'a> CONDRST_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `CONFIGLOCK`"] pub type CONFIGLOCK_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CONFIGLOCK`"] pub struct CONFIGLOCK_W<'a> { w: &'a mut W, } impl<'a> CONFIGLOCK_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bit 2 - Random number generator enable"] #[inline(always)] pub fn rngen(&self) -> RNGEN_R { RNGEN_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - Interrupt enable"] #[inline(always)] pub fn ie(&self) -> IE_R { IE_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 5 - Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled."] #[inline(always)] pub fn ced(&self) -> CED_R { CED_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bits 8:11 - RNG configuration 3"] #[inline(always)] pub fn rng_config3(&self) -> RNG_CONFIG3_R { RNG_CONFIG3_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - Non NIST compliant"] #[inline(always)] pub fn nistc(&self) -> NISTC_R { NISTC_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bits 13:15 - RNG configuration 2"] #[inline(always)] pub fn rng_config2(&self) -> RNG_CONFIG2_R { RNG_CONFIG2_R::new(((self.bits >> 13) & 0x07) as u8) } #[doc = "Bits 16:19 - Clock divider factor"] #[inline(always)] pub fn clkdiv(&self) -> CLKDIV_R { CLKDIV_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bits 20:25 - RNG configuration 1"] #[inline(always)] pub fn rng_config1(&self) -> RNG_CONFIG1_R { RNG_CONFIG1_R::new(((self.bits >> 20) & 0x3f) as u8) } #[doc = "Bit 30 - Conditioning soft reset"] #[inline(always)] pub fn condrst(&self) -> CONDRST_R { CONDRST_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - RNG Config Lock"] #[inline(always)] pub fn configlock(&self) -> CONFIGLOCK_R { CONFIGLOCK_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bit 2 - Random number generator enable"] #[inline(always)] pub fn rngen(&mut self) -> RNGEN_W { RNGEN_W { w: self } } #[doc = "Bit 3 - Interrupt enable"] #[inline(always)] pub fn ie(&mut self) -> IE_W { IE_W { w: self } } #[doc = "Bit 5 - Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled."] #[inline(always)] pub fn ced(&mut self) -> CED_W { CED_W { w: self } } #[doc = "Bits 8:11 - RNG configuration 3"] #[inline(always)] pub fn rng_config3(&mut self) -> RNG_CONFIG3_W { RNG_CONFIG3_W { w: self } } #[doc = "Bit 12 - Non NIST compliant"] #[inline(always)] pub fn nistc(&mut self) -> NISTC_W { NISTC_W { w: self } } #[doc = "Bits 13:15 - RNG configuration 2"] #[inline(always)] pub fn rng_config2(&mut self) -> RNG_CONFIG2_W { RNG_CONFIG2_W { w: self } } #[doc = "Bits 16:19 - Clock divider factor"] #[inline(always)] pub fn clkdiv(&mut self) -> CLKDIV_W { CLKDIV_W { w: self } } #[doc = "Bits 20:25 - RNG configuration 1"] #[inline(always)] pub fn rng_config1(&mut self) -> RNG_CONFIG1_W { RNG_CONFIG1_W { w: self } } #[doc = "Bit 30 - Conditioning soft reset"] #[inline(always)] pub fn condrst(&mut self) -> CONDRST_W { CONDRST_W { w: self } } #[doc = "Bit 31 - RNG Config Lock"] #[inline(always)] pub fn configlock(&mut self) -> CONFIGLOCK_W { CONFIGLOCK_W { w: self } } }