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#[doc = "Reader of register DAC_CR"] pub type R = crate::R<u32, super::DAC_CR>; #[doc = "Writer for register DAC_CR"] pub type W = crate::W<u32, super::DAC_CR>; #[doc = "Register DAC_CR `reset()`'s with value 0"] impl crate::ResetValue for super::DAC_CR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `EN1`"] pub type EN1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `EN1`"] pub struct EN1_W<'a> { w: &'a mut W, } impl<'a> EN1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `TEN1`"] pub type TEN1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TEN1`"] pub struct TEN1_W<'a> { w: &'a mut W, } impl<'a> TEN1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `TSEL10`"] pub type TSEL10_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL10`"] pub struct TSEL10_W<'a> { w: &'a mut W, } impl<'a> TSEL10_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `TSEL11`"] pub type TSEL11_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL11`"] pub struct TSEL11_W<'a> { w: &'a mut W, } impl<'a> TSEL11_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `TSEL12`"] pub type TSEL12_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL12`"] pub struct TSEL12_W<'a> { w: &'a mut W, } impl<'a> TSEL12_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "Reader of field `TSEL13`"] pub type TSEL13_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL13`"] pub struct TSEL13_W<'a> { w: &'a mut W, } impl<'a> TSEL13_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = "Reader of field `WAVE1`"] pub type WAVE1_R = crate::R<u8, u8>; #[doc = "Write proxy for field `WAVE1`"] pub struct WAVE1_W<'a> { w: &'a mut W, } impl<'a> WAVE1_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6); self.w } } #[doc = "Reader of field `MAMP1`"] pub type MAMP1_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MAMP1`"] pub struct MAMP1_W<'a> { w: &'a mut W, } impl<'a> MAMP1_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); self.w } } #[doc = "Reader of field `DMAEN1`"] pub type DMAEN1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAEN1`"] pub struct DMAEN1_W<'a> { w: &'a mut W, } impl<'a> DMAEN1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `DMAUDRIE1`"] pub type DMAUDRIE1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAUDRIE1`"] pub struct DMAUDRIE1_W<'a> { w: &'a mut W, } impl<'a> DMAUDRIE1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Reader of field `CEN1`"] pub type CEN1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CEN1`"] pub struct CEN1_W<'a> { w: &'a mut W, } impl<'a> CEN1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); self.w } } #[doc = "Reader of field `HFSEL`"] pub type HFSEL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HFSEL`"] pub struct HFSEL_W<'a> { w: &'a mut W, } impl<'a> HFSEL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `EN2`"] pub type EN2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `EN2`"] pub struct EN2_W<'a> { w: &'a mut W, } impl<'a> EN2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `TEN2`"] pub type TEN2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TEN2`"] pub struct TEN2_W<'a> { w: &'a mut W, } impl<'a> TEN2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `TSEL20`"] pub type TSEL20_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL20`"] pub struct TSEL20_W<'a> { w: &'a mut W, } impl<'a> TSEL20_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); self.w } } #[doc = "Reader of field `TSEL21`"] pub type TSEL21_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL21`"] pub struct TSEL21_W<'a> { w: &'a mut W, } impl<'a> TSEL21_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); self.w } } #[doc = "Reader of field `TSEL22`"] pub type TSEL22_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL22`"] pub struct TSEL22_W<'a> { w: &'a mut W, } impl<'a> TSEL22_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); self.w } } #[doc = "Reader of field `TSEL23`"] pub type TSEL23_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSEL23`"] pub struct TSEL23_W<'a> { w: &'a mut W, } impl<'a> TSEL23_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); self.w } } #[doc = "Reader of field `WAVE2`"] pub type WAVE2_R = crate::R<u8, u8>; #[doc = "Write proxy for field `WAVE2`"] pub struct WAVE2_W<'a> { w: &'a mut W, } impl<'a> WAVE2_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22); self.w } } #[doc = "Reader of field `MAMP2`"] pub type MAMP2_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MAMP2`"] pub struct MAMP2_W<'a> { w: &'a mut W, } impl<'a> MAMP2_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24); self.w } } #[doc = "Reader of field `DMAEN2`"] pub type DMAEN2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAEN2`"] pub struct DMAEN2_W<'a> { w: &'a mut W, } impl<'a> DMAEN2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Reader of field `DMAUDRIE2`"] pub type DMAUDRIE2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAUDRIE2`"] pub struct DMAUDRIE2_W<'a> { w: &'a mut W, } impl<'a> DMAUDRIE2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); self.w } } #[doc = "Reader of field `CEN2`"] pub type CEN2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CEN2`"] pub struct CEN2_W<'a> { w: &'a mut W, } impl<'a> CEN2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } impl R { #[doc = "Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1."] #[inline(always)] pub fn en1(&self) -> EN1_R { EN1_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - DAC channel1 trigger enable"] #[inline(always)] pub fn ten1(&self) -> TEN1_R { TEN1_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 2 - TSEL10"] #[inline(always)] pub fn tsel10(&self) -> TSEL10_R { TSEL10_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - TSEL11"] #[inline(always)] pub fn tsel11(&self) -> TSEL11_R { TSEL11_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 4 - TSEL12"] #[inline(always)] pub fn tsel12(&self) -> TSEL12_R { TSEL12_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 5 - TSEL13"] #[inline(always)] pub fn tsel13(&self) -> TSEL13_R { TSEL13_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)."] #[inline(always)] pub fn wave1(&self) -> WAVE1_R { WAVE1_R::new(((self.bits >> 6) & 0x03) as u8) } #[doc = "Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits\\[11:0\\] of LFSR/ triangle amplitude equal to 4095"] #[inline(always)] pub fn mamp1(&self) -> MAMP1_R { MAMP1_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaen1(&self) -> DMAEN1_R { DMAEN1_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaudrie1(&self) -> DMAUDRIE1_R { DMAUDRIE1_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bit 14 - DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored."] #[inline(always)] pub fn cen1(&self) -> CEN1_R { CEN1_R::new(((self.bits >> 14) & 0x01) != 0) } #[doc = "Bit 15 - HFSEL"] #[inline(always)] pub fn hfsel(&self) -> HFSEL_R { HFSEL_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2."] #[inline(always)] pub fn en2(&self) -> EN2_R { EN2_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 17 - DAC channel2 trigger enable"] #[inline(always)] pub fn ten2(&self) -> TEN2_R { TEN2_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bit 18 - TSEL20"] #[inline(always)] pub fn tsel20(&self) -> TSEL20_R { TSEL20_R::new(((self.bits >> 18) & 0x01) != 0) } #[doc = "Bit 19 - TSEL21"] #[inline(always)] pub fn tsel21(&self) -> TSEL21_R { TSEL21_R::new(((self.bits >> 19) & 0x01) != 0) } #[doc = "Bit 20 - TSEL22"] #[inline(always)] pub fn tsel22(&self) -> TSEL22_R { TSEL22_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bit 21 - TSEL23"] #[inline(always)] pub fn tsel23(&self) -> TSEL23_R { TSEL23_R::new(((self.bits >> 21) & 0x01) != 0) } #[doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)"] #[inline(always)] pub fn wave2(&self) -> WAVE2_R { WAVE2_R::new(((self.bits >> 22) & 0x03) as u8) } #[doc = "Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits\\[11:0\\] of LFSR/ triangle amplitude equal to 4095"] #[inline(always)] pub fn mamp2(&self) -> MAMP2_R { MAMP2_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaen2(&self) -> DMAEN2_R { DMAEN2_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaudrie2(&self) -> DMAUDRIE2_R { DMAUDRIE2_R::new(((self.bits >> 29) & 0x01) != 0) } #[doc = "Bit 30 - DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored."] #[inline(always)] pub fn cen2(&self) -> CEN2_R { CEN2_R::new(((self.bits >> 30) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1."] #[inline(always)] pub fn en1(&mut self) -> EN1_W { EN1_W { w: self } } #[doc = "Bit 1 - DAC channel1 trigger enable"] #[inline(always)] pub fn ten1(&mut self) -> TEN1_W { TEN1_W { w: self } } #[doc = "Bit 2 - TSEL10"] #[inline(always)] pub fn tsel10(&mut self) -> TSEL10_W { TSEL10_W { w: self } } #[doc = "Bit 3 - TSEL11"] #[inline(always)] pub fn tsel11(&mut self) -> TSEL11_W { TSEL11_W { w: self } } #[doc = "Bit 4 - TSEL12"] #[inline(always)] pub fn tsel12(&mut self) -> TSEL12_W { TSEL12_W { w: self } } #[doc = "Bit 5 - TSEL13"] #[inline(always)] pub fn tsel13(&mut self) -> TSEL13_W { TSEL13_W { w: self } } #[doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)."] #[inline(always)] pub fn wave1(&mut self) -> WAVE1_W { WAVE1_W { w: self } } #[doc = "Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits\\[11:0\\] of LFSR/ triangle amplitude equal to 4095"] #[inline(always)] pub fn mamp1(&mut self) -> MAMP1_W { MAMP1_W { w: self } } #[doc = "Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaen1(&mut self) -> DMAEN1_W { DMAEN1_W { w: self } } #[doc = "Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W { DMAUDRIE1_W { w: self } } #[doc = "Bit 14 - DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored."] #[inline(always)] pub fn cen1(&mut self) -> CEN1_W { CEN1_W { w: self } } #[doc = "Bit 15 - HFSEL"] #[inline(always)] pub fn hfsel(&mut self) -> HFSEL_W { HFSEL_W { w: self } } #[doc = "Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2."] #[inline(always)] pub fn en2(&mut self) -> EN2_W { EN2_W { w: self } } #[doc = "Bit 17 - DAC channel2 trigger enable"] #[inline(always)] pub fn ten2(&mut self) -> TEN2_W { TEN2_W { w: self } } #[doc = "Bit 18 - TSEL20"] #[inline(always)] pub fn tsel20(&mut self) -> TSEL20_W { TSEL20_W { w: self } } #[doc = "Bit 19 - TSEL21"] #[inline(always)] pub fn tsel21(&mut self) -> TSEL21_W { TSEL21_W { w: self } } #[doc = "Bit 20 - TSEL22"] #[inline(always)] pub fn tsel22(&mut self) -> TSEL22_W { TSEL22_W { w: self } } #[doc = "Bit 21 - TSEL23"] #[inline(always)] pub fn tsel23(&mut self) -> TSEL23_W { TSEL23_W { w: self } } #[doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)"] #[inline(always)] pub fn wave2(&mut self) -> WAVE2_W { WAVE2_W { w: self } } #[doc = "Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits\\[11:0\\] of LFSR/ triangle amplitude equal to 4095"] #[inline(always)] pub fn mamp2(&mut self) -> MAMP2_W { MAMP2_W { w: self } } #[doc = "Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaen2(&mut self) -> DMAEN2_W { DMAEN2_W { w: self } } #[doc = "Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software."] #[inline(always)] pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W { DMAUDRIE2_W { w: self } } #[doc = "Bit 30 - DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored."] #[inline(always)] pub fn cen2(&mut self) -> CEN2_W { CEN2_W { w: self } } }