Expand description

Reset and Clock Control

Structs

Advanced High-performance Bus 1 (AHB1) registers

Advanced High-performance Bus 2 (AHB2) registers

Advanced High-performance Bus 3 (AHB3) registers

Advanced Peripheral Bus 1 (APB1) registers

Advanced Peripheral Bus 1 (APB1) registers

Advanced Peripheral Bus 2 (APB2) registers

BDCR Backup domain control register registers

Peripherals independent clock configuration register

Clock configuration

Clock recovery RC register

CSR Control/Status Register

Frozen clock frequencies

PLL Configuration

Constrained RCC peripheral

Enums

Clock Security System (CSS) selector

Crystal bypass selector

PLL output divider options

PLL Source

Traits

Enable/disable peripheral

Bus associated to peripheral

Extension trait that constrains the RCC peripheral

Reset peripheral

Enable/disable peripheral in sleep mode