Expand description
PLL configuration register
Structs
PLL configuration register
Field PLLM
reader - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Field PLLM
writer - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Field PLLN
reader - Main PLL multiplication factor for VCO
Field PLLN
writer - Main PLL multiplication factor for VCO
Field PLLPDIV
reader - Main PLL division factor for PLLSAI2CLK
Field PLLPDIV
writer - Main PLL division factor for PLLSAI2CLK
Field PLLPEN
reader - Main PLL PLLSAI3CLK output enable
Field PLLPEN
writer - Main PLL PLLSAI3CLK output enable
Field PLLP
reader - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
Field PLLP
writer - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
Field PLLQEN
reader - Main PLL PLLUSB1CLK output enable
Field PLLQEN
writer - Main PLL PLLUSB1CLK output enable
Field PLLQ
reader - Main PLL division factor for PLLUSB1CLK(48 MHz clock)
Field PLLQ
writer - Main PLL division factor for PLLUSB1CLK(48 MHz clock)
Field PLLREN
reader - Main PLL PLLCLK output enable
Field PLLREN
writer - Main PLL PLLCLK output enable
Field PLLR
reader - Main PLL division factor for PLLCLK (system clock)
Field PLLR
writer - Main PLL division factor for PLLCLK (system clock)
Field PLLSRC
reader - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
Field PLLSRC
writer - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
Register PLLCFGR
reader
Register PLLCFGR
writer