Expand description
control register 1
Structs
Type Definitions
Field AWFSEL
reader - Analog watchdog fast mode select
Field AWFSEL
writer - Analog watchdog fast mode select
Field DFEN
reader - DFSDM enable
Field DFEN
writer - DFSDM enable
Field FAST
reader - Fast conversion mode selection for regular conversions
Field FAST
writer - Fast conversion mode selection for regular conversions
Field JDMAEN
reader - DMA channel enabled to read data for the injected channel group
Field JDMAEN
writer - DMA channel enabled to read data for the injected channel group
Field JEXTEN
reader - Trigger enable and trigger edge selection for injected conversions
Field JEXTEN
writer - Trigger enable and trigger edge selection for injected conversions
Field JEXTSEL
reader - Trigger signal selection for launching injected conversions
Field JEXTSEL
writer - Trigger signal selection for launching injected conversions
Field JSCAN
reader - Scanning conversion mode for injected conversions
Field JSCAN
writer - Scanning conversion mode for injected conversions
Field JSWSTART
reader - Start a conversion of the injected group of channels
Field JSWSTART
writer - Start a conversion of the injected group of channels
Field JSYNC
reader - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
Field JSYNC
writer - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
Field RCH
reader - Regular channel selection
Field RCH
writer - Regular channel selection
Field RCONT
reader - Continuous mode selection for regular conversions
Field RCONT
writer - Continuous mode selection for regular conversions
Field RDMAEN
reader - DMA channel enabled to read data for the regular conversion
Field RDMAEN
writer - DMA channel enabled to read data for the regular conversion
Field RSWSTART
reader - Software start of a conversion on the regular channel
Field RSWSTART
writer - Software start of a conversion on the regular channel
Field RSYNC
reader - Launch regular conversion synchronously with DFSDM0
Field RSYNC
writer - Launch regular conversion synchronously with DFSDM0