Struct stm32l151::adc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub sr: SR,
    pub cr1: CR1,
    pub cr2: CR2,
    pub smpr1: SMPR1,
    pub smpr2: SMPR2,
    pub smpr3: SMPR3,
    pub jofr1: JOFR1,
    pub jofr2: JOFR2,
    pub jofr3: JOFR3,
    pub jofr4: JOFR4,
    pub htr: HTR,
    pub ltr: LTR,
    pub sqr1: SQR1,
    pub sqr2: SQR2,
    pub sqr3: SQR3,
    pub sqr4: SQR4,
    pub sqr5: SQR5,
    pub jsqr: JSQR,
    pub jdr1: JDR1,
    pub jdr2: JDR2,
    pub jdr3: JDR3,
    pub jdr4: JDR4,
    pub dr: DR,
    pub smpr0: SMPR0,
    pub csr: CSR,
    pub ccr: CCR,
    // some fields omitted
}

Register block

Fields

sr: SR

0x00 - status register

cr1: CR1

0x04 - control register 1

cr2: CR2

0x08 - control register 2

smpr1: SMPR1

0x0c - sample time register 1

smpr2: SMPR2

0x10 - sample time register 2

smpr3: SMPR3

0x14 - sample time register 3

jofr1: JOFR1

0x18 - injected channel data offset register x

jofr2: JOFR2

0x1c - injected channel data offset register x

jofr3: JOFR3

0x20 - injected channel data offset register x

jofr4: JOFR4

0x24 - injected channel data offset register x

htr: HTR

0x28 - watchdog higher threshold register

ltr: LTR

0x2c - watchdog lower threshold register

sqr1: SQR1

0x30 - regular sequence register 1

sqr2: SQR2

0x34 - regular sequence register 2

sqr3: SQR3

0x38 - regular sequence register 3

sqr4: SQR4

0x3c - regular sequence register 4

sqr5: SQR5

0x40 - regular sequence register 5

jsqr: JSQR

0x44 - injected sequence register

jdr1: JDR1

0x48 - injected data register x

jdr2: JDR2

0x4c - injected data register x

jdr3: JDR3

0x50 - injected data register x

jdr4: JDR4

0x54 - injected data register x

dr: DR

0x58 - regular data register

smpr0: SMPR0

0x5c - sample time register 0

csr: CSR

0x300 - ADC common status register

ccr: CCR

0x304 - ADC common control register