Module stm32h7xx_hal::stm32::rng::cr

RNG control register

Structs

CED_W	Write proxy for field CED
IE_W	Write proxy for field IE
RNGEN_W	Write proxy for field RNGEN

Enums

CED_A	Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled.
IE_A	Interrupt enable
RNGEN_A	Random number generator enable

Type Definitions

CED_R	Reader of field CED
IE_R	Reader of field IE
R	Reader of register CR
RNGEN_R	Reader of field RNGEN
W	Writer for register CR