Struct stm32h7xx_hal::stm32::rcc::RegisterBlock [−][src]
Register block
Fields
cr: Reg<u32, _CR>
0x00 - clock control register
crrcr: Reg<u32, _CRRCR>
0x08 - RCC Clock Recovery RC Register
csicfgr: Reg<u32, _CSICFGR>
0x0c - RCC CSI configuration register
cfgr: Reg<u32, _CFGR>
0x10 - RCC Clock Configuration Register
d1cfgr: Reg<u32, _D1CFGR>
0x18 - RCC Domain 1 Clock Configuration Register
d2cfgr: Reg<u32, _D2CFGR>
0x1c - RCC Domain 2 Clock Configuration Register
d3cfgr: Reg<u32, _D3CFGR>
0x20 - RCC Domain 3 Clock Configuration Register
pllckselr: Reg<u32, _PLLCKSELR>
0x28 - RCC PLLs Clock Source Selection Register
pllcfgr: Reg<u32, _PLLCFGR>
0x2c - RCC PLLs Configuration Register
pll1divr: Reg<u32, _PLL1DIVR>
0x30 - RCC PLL1 Dividers Configuration Register
pll1fracr: Reg<u32, _PLL1FRACR>
0x34 - RCC PLL1 Fractional Divider Register
pll2divr: Reg<u32, _PLL2DIVR>
0x38 - RCC PLL2 Dividers Configuration Register
pll2fracr: Reg<u32, _PLL2FRACR>
0x3c - RCC PLL2 Fractional Divider Register
pll3divr: Reg<u32, _PLL3DIVR>
0x40 - RCC PLL3 Dividers Configuration Register
pll3fracr: Reg<u32, _PLL3FRACR>
0x44 - RCC PLL3 Fractional Divider Register
d1ccipr: Reg<u32, _D1CCIPR>
0x4c - RCC Domain 1 Kernel Clock Configuration Register
d2ccip1r: Reg<u32, _D2CCIP1R>
0x50 - RCC Domain 2 Kernel Clock Configuration Register
d2ccip2r: Reg<u32, _D2CCIP2R>
0x54 - RCC Domain 2 Kernel Clock Configuration Register
d3ccipr: Reg<u32, _D3CCIPR>
0x58 - RCC Domain 3 Kernel Clock Configuration Register
cier: Reg<u32, _CIER>
0x60 - RCC Clock Source Interrupt Enable Register
cifr: Reg<u32, _CIFR>
0x64 - RCC Clock Source Interrupt Flag Register
cicr: Reg<u32, _CICR>
0x68 - RCC Clock Source Interrupt Clear Register
bdcr: Reg<u32, _BDCR>
0x70 - RCC Backup Domain Control Register
csr: Reg<u32, _CSR>
0x74 - RCC Clock Control and Status Register
ahb3rstr: Reg<u32, _AHB3RSTR>
0x7c - RCC AHB3 Reset Register
ahb1rstr: Reg<u32, _AHB1RSTR>
0x80 - RCC AHB1 Peripheral Reset Register
ahb2rstr: Reg<u32, _AHB2RSTR>
0x84 - RCC AHB2 Peripheral Reset Register
ahb4rstr: Reg<u32, _AHB4RSTR>
0x88 - RCC AHB4 Peripheral Reset Register
apb3rstr: Reg<u32, _APB3RSTR>
0x8c - RCC APB3 Peripheral Reset Register
apb1lrstr: Reg<u32, _APB1LRSTR>
0x90 - RCC APB1 Peripheral Reset Register
apb1hrstr: Reg<u32, _APB1HRSTR>
0x94 - RCC APB1 Peripheral Reset Register
apb2rstr: Reg<u32, _APB2RSTR>
0x98 - RCC APB2 Peripheral Reset Register
apb4rstr: Reg<u32, _APB4RSTR>
0x9c - RCC APB4 Peripheral Reset Register
gcr: Reg<u32, _GCR>
0xa0 - RCC Global Control Register
d3amr: Reg<u32, _D3AMR>
0xa8 - RCC D3 Autonomous mode Register
rsr: Reg<u32, _RSR>
0xd0 - RCC Reset Status Register
ahb3enr: Reg<u32, _AHB3ENR>
0xd4 - RCC AHB3 Clock Register
ahb1enr: Reg<u32, _AHB1ENR>
0xd8 - RCC AHB1 Clock Register
ahb2enr: Reg<u32, _AHB2ENR>
0xdc - RCC AHB2 Clock Register
ahb4enr: Reg<u32, _AHB4ENR>
0xe0 - RCC AHB4 Clock Register
apb3enr: Reg<u32, _APB3ENR>
0xe4 - RCC APB3 Clock Register
apb1lenr: Reg<u32, _APB1LENR>
0xe8 - RCC APB1 Clock Register
apb1henr: Reg<u32, _APB1HENR>
0xec - RCC APB1 Clock Register
apb2enr: Reg<u32, _APB2ENR>
0xf0 - RCC APB2 Clock Register
apb4enr: Reg<u32, _APB4ENR>
0xf4 - RCC APB4 Clock Register
ahb3lpenr: Reg<u32, _AHB3LPENR>
0xfc - RCC AHB3 Sleep Clock Register
ahb1lpenr: Reg<u32, _AHB1LPENR>
0x100 - RCC AHB1 Sleep Clock Register
ahb2lpenr: Reg<u32, _AHB2LPENR>
0x104 - RCC AHB2 Sleep Clock Register
ahb4lpenr: Reg<u32, _AHB4LPENR>
0x108 - RCC AHB4 Sleep Clock Register
apb3lpenr: Reg<u32, _APB3LPENR>
0x10c - RCC APB3 Sleep Clock Register
apb1llpenr: Reg<u32, _APB1LLPENR>
0x110 - RCC APB1 Low Sleep Clock Register
apb1hlpenr: Reg<u32, _APB1HLPENR>
0x114 - RCC APB1 High Sleep Clock Register
apb2lpenr: Reg<u32, _APB2LPENR>
0x118 - RCC APB2 Sleep Clock Register
apb4lpenr: Reg<u32, _APB4LPENR>
0x11c - RCC APB4 Sleep Clock Register
c1_rsr: Reg<u32, _C1_RSR>
0x130 - RCC Reset Status Register
c1_ahb3enr: Reg<u32, _C1_AHB3ENR>
0x134 - RCC AHB3 Clock Register
c1_ahb1enr: Reg<u32, _C1_AHB1ENR>
0x138 - RCC AHB1 Clock Register
c1_ahb2enr: Reg<u32, _C1_AHB2ENR>
0x13c - RCC AHB2 Clock Register
c1_ahb4enr: Reg<u32, _C1_AHB4ENR>
0x140 - RCC AHB4 Clock Register
c1_apb3enr: Reg<u32, _C1_APB3ENR>
0x144 - RCC APB3 Clock Register
c1_apb1lenr: Reg<u32, _C1_APB1LENR>
0x148 - RCC APB1 Clock Register
c1_apb1henr: Reg<u32, _C1_APB1HENR>
0x14c - RCC APB1 Clock Register
c1_apb2enr: Reg<u32, _C1_APB2ENR>
0x150 - RCC APB2 Clock Register
c1_apb4enr: Reg<u32, _C1_APB4ENR>
0x154 - RCC APB4 Clock Register
c1_ahb3lpenr: Reg<u32, _C1_AHB3LPENR>
0x15c - RCC AHB3 Sleep Clock Register
c1_ahb1lpenr: Reg<u32, _C1_AHB1LPENR>
0x160 - RCC AHB1 Sleep Clock Register
c1_ahb2lpenr: Reg<u32, _C1_AHB2LPENR>
0x164 - RCC AHB2 Sleep Clock Register
c1_ahb4lpenr: Reg<u32, _C1_AHB4LPENR>
0x168 - RCC AHB4 Sleep Clock Register
c1_apb3lpenr: Reg<u32, _C1_APB3LPENR>
0x16c - RCC APB3 Sleep Clock Register
c1_apb1llpenr: Reg<u32, _C1_APB1LLPENR>
0x170 - RCC APB1 Low Sleep Clock Register
c1_apb1hlpenr: Reg<u32, _C1_APB1HLPENR>
0x174 - RCC APB1 High Sleep Clock Register
c1_apb2lpenr: Reg<u32, _C1_APB2LPENR>
0x178 - RCC APB2 Sleep Clock Register
c1_apb4lpenr: Reg<u32, _C1_APB4LPENR>
0x17c - RCC APB4 Sleep Clock Register
Implementations
impl RegisterBlock
[src]
pub fn hsicfgr(&self) -> &Reg<u32, _HSICFGR>
[src]
0x04 - RCC HSI configuration register
pub fn hsicfgr_mut(&self) -> &mut Reg<u32, _HSICFGR>
[src]
0x04 - RCC HSI configuration register
pub fn icscr(&self) -> &Reg<u32, _ICSCR>
[src]
0x04 - RCC Internal Clock Source Calibration Register
pub fn icscr_mut(&self) -> &mut Reg<u32, _ICSCR>
[src]
0x04 - RCC Internal Clock Source Calibration Register
Auto Trait Implementations
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impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
pub fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
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U: Into<T>,
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impl<T, U> TryInto<U> for T where
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