Module stm32h7xx_hal::stm32::i2c1::timeoutr

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Structs

TEXTEN_W	Write proxy for field TEXTEN
TIDLE_W	Write proxy for field TIDLE
TIMEOUTA_W	Write proxy for field TIMEOUTA
TIMEOUTB_W	Write proxy for field TIMEOUTB
TIMOUTEN_W	Write proxy for field TIMOUTEN

Enums

TEXTEN_A	Extended clock timeout enable
TIDLE_A	Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
TIMOUTEN_A	Clock timeout enable

Type Definitions

R	Reader of register TIMEOUTR
TEXTEN_R	Reader of field TEXTEN
TIDLE_R	Reader of field TIDLE
TIMEOUTA_R	Reader of field TIMEOUTA
TIMEOUTB_R	Reader of field TIMEOUTB
TIMOUTEN_R	Reader of field TIMOUTEN
W	Writer for register TIMEOUTR