Module stm32h7xx_hal::stm32::i2c1::oar1 [−][src]
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
Structs
| OA1EN_W | Write proxy for field |
| OA1MODE_W | Write proxy for field |
| OA1_W | Write proxy for field |
Enums
| OA1EN_A | Own Address 1 enable |
| OA1MODE_A | Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0. |
Type Definitions
| OA1EN_R | Reader of field |
| OA1MODE_R | Reader of field |
| OA1_R | Reader of field |
| R | Reader of register OAR1 |
| W | Writer for register OAR1 |