Module stm32h7xx_hal::stm32::i2c1::cr2 [−][src]
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
Structs
| ADD10_W | Write proxy for field |
| AUTOEND_W | Write proxy for field |
| HEAD10R_W | Write proxy for field |
| NACK_W | Write proxy for field |
| NBYTES_W | Write proxy for field |
| PECBYTE_W | Write proxy for field |
| RD_WRN_W | Write proxy for field |
| RELOAD_W | Write proxy for field |
| SADD_W | Write proxy for field |
| START_W | Write proxy for field |
| STOP_W | Write proxy for field |
Enums
| ADD10_A | 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. |
| AUTOEND_A | Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. |
| HEAD10R_A | 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. |
| NACK_A | NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. |
| PECBYTE_A | Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. |
| RD_WRN_A | Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. |
| RELOAD_A | NBYTES reload mode This bit is set and cleared by software. |
| START_A | Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set. |
| STOP_A | Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect. |
Type Definitions
| ADD10_R | Reader of field |
| AUTOEND_R | Reader of field |
| HEAD10R_R | Reader of field |
| NACK_R | Reader of field |
| NBYTES_R | Reader of field |
| PECBYTE_R | Reader of field |
| R | Reader of register CR2 |
| RD_WRN_R | Reader of field |
| RELOAD_R | Reader of field |
| SADD_R | Reader of field |
| START_R | Reader of field |
| STOP_R | Reader of field |
| W | Writer for register CR2 |