Struct stm32h7xx_hal::stm32::hsem::RegisterBlock[][src]

#[repr(C)]pub struct RegisterBlock {
    pub r0: Reg<u32, _R0>,
    pub r1: Reg<u32, _R1>,
    pub r2: Reg<u32, _R2>,
    pub r3: Reg<u32, _R3>,
    pub r4: Reg<u32, _R4>,
    pub r5: Reg<u32, _R5>,
    pub r6: Reg<u32, _R6>,
    pub r7: Reg<u32, _R7>,
    pub r8: Reg<u32, _R8>,
    pub r9: Reg<u32, _R9>,
    pub r10: Reg<u32, _R10>,
    pub r11: Reg<u32, _R11>,
    pub r12: Reg<u32, _R12>,
    pub r13: Reg<u32, _R13>,
    pub r14: Reg<u32, _R14>,
    pub r15: Reg<u32, _R15>,
    pub r16: Reg<u32, _R16>,
    pub r17: Reg<u32, _R17>,
    pub r18: Reg<u32, _R18>,
    pub r19: Reg<u32, _R19>,
    pub r20: Reg<u32, _R20>,
    pub r21: Reg<u32, _R21>,
    pub r22: Reg<u32, _R22>,
    pub r23: Reg<u32, _R23>,
    pub r24: Reg<u32, _R24>,
    pub r25: Reg<u32, _R25>,
    pub r26: Reg<u32, _R26>,
    pub r27: Reg<u32, _R27>,
    pub r28: Reg<u32, _R28>,
    pub r29: Reg<u32, _R29>,
    pub r30: Reg<u32, _R30>,
    pub r31: Reg<u32, _R31>,
    pub rlr0: Reg<u32, _RLR0>,
    pub rlr1: Reg<u32, _RLR1>,
    pub rlr2: Reg<u32, _RLR2>,
    pub rlr3: Reg<u32, _RLR3>,
    pub rlr4: Reg<u32, _RLR4>,
    pub rlr5: Reg<u32, _RLR5>,
    pub rlr6: Reg<u32, _RLR6>,
    pub rlr7: Reg<u32, _RLR7>,
    pub rlr8: Reg<u32, _RLR8>,
    pub rlr9: Reg<u32, _RLR9>,
    pub rlr10: Reg<u32, _RLR10>,
    pub rlr11: Reg<u32, _RLR11>,
    pub rlr12: Reg<u32, _RLR12>,
    pub rlr13: Reg<u32, _RLR13>,
    pub rlr14: Reg<u32, _RLR14>,
    pub rlr15: Reg<u32, _RLR15>,
    pub rlr16: Reg<u32, _RLR16>,
    pub rlr17: Reg<u32, _RLR17>,
    pub rlr18: Reg<u32, _RLR18>,
    pub rlr19: Reg<u32, _RLR19>,
    pub rlr20: Reg<u32, _RLR20>,
    pub rlr21: Reg<u32, _RLR21>,
    pub rlr22: Reg<u32, _RLR22>,
    pub rlr23: Reg<u32, _RLR23>,
    pub rlr24: Reg<u32, _RLR24>,
    pub rlr25: Reg<u32, _RLR25>,
    pub rlr26: Reg<u32, _RLR26>,
    pub rlr27: Reg<u32, _RLR27>,
    pub rlr28: Reg<u32, _RLR28>,
    pub rlr29: Reg<u32, _RLR29>,
    pub rlr30: Reg<u32, _RLR30>,
    pub rlr31: Reg<u32, _RLR31>,
    pub ier: Reg<u32, _IER>,
    pub icr: Reg<u32, _ICR>,
    pub isr: Reg<u32, _ISR>,
    pub misr: Reg<u32, _MISR>,
    pub cr: Reg<u32, _CR>,
    pub keyr: Reg<u32, _KEYR>,
    // some fields omitted
}

Register block

Fields

r0: Reg<u32, _R0>

0x00 - HSEM register HSEM_R0 HSEM_R31

r1: Reg<u32, _R1>

0x04 - HSEM register HSEM_R0 HSEM_R31

r2: Reg<u32, _R2>

0x08 - HSEM register HSEM_R0 HSEM_R31

r3: Reg<u32, _R3>

0x0c - HSEM register HSEM_R0 HSEM_R31

r4: Reg<u32, _R4>

0x10 - HSEM register HSEM_R0 HSEM_R31

r5: Reg<u32, _R5>

0x14 - HSEM register HSEM_R0 HSEM_R31

r6: Reg<u32, _R6>

0x18 - HSEM register HSEM_R0 HSEM_R31

r7: Reg<u32, _R7>

0x1c - HSEM register HSEM_R0 HSEM_R31

r8: Reg<u32, _R8>

0x20 - HSEM register HSEM_R0 HSEM_R31

r9: Reg<u32, _R9>

0x24 - HSEM register HSEM_R0 HSEM_R31

r10: Reg<u32, _R10>

0x28 - HSEM register HSEM_R0 HSEM_R31

r11: Reg<u32, _R11>

0x2c - HSEM register HSEM_R0 HSEM_R31

r12: Reg<u32, _R12>

0x30 - HSEM register HSEM_R0 HSEM_R31

r13: Reg<u32, _R13>

0x34 - HSEM register HSEM_R0 HSEM_R31

r14: Reg<u32, _R14>

0x38 - HSEM register HSEM_R0 HSEM_R31

r15: Reg<u32, _R15>

0x3c - HSEM register HSEM_R0 HSEM_R31

r16: Reg<u32, _R16>

0x40 - HSEM register HSEM_R0 HSEM_R31

r17: Reg<u32, _R17>

0x44 - HSEM register HSEM_R0 HSEM_R31

r18: Reg<u32, _R18>

0x48 - HSEM register HSEM_R0 HSEM_R31

r19: Reg<u32, _R19>

0x4c - HSEM register HSEM_R0 HSEM_R31

r20: Reg<u32, _R20>

0x50 - HSEM register HSEM_R0 HSEM_R31

r21: Reg<u32, _R21>

0x54 - HSEM register HSEM_R0 HSEM_R31

r22: Reg<u32, _R22>

0x58 - HSEM register HSEM_R0 HSEM_R31

r23: Reg<u32, _R23>

0x5c - HSEM register HSEM_R0 HSEM_R31

r24: Reg<u32, _R24>

0x60 - HSEM register HSEM_R0 HSEM_R31

r25: Reg<u32, _R25>

0x64 - HSEM register HSEM_R0 HSEM_R31

r26: Reg<u32, _R26>

0x68 - HSEM register HSEM_R0 HSEM_R31

r27: Reg<u32, _R27>

0x6c - HSEM register HSEM_R0 HSEM_R31

r28: Reg<u32, _R28>

0x70 - HSEM register HSEM_R0 HSEM_R31

r29: Reg<u32, _R29>

0x74 - HSEM register HSEM_R0 HSEM_R31

r30: Reg<u32, _R30>

0x78 - HSEM register HSEM_R0 HSEM_R31

r31: Reg<u32, _R31>

0x7c - HSEM register HSEM_R0 HSEM_R31

rlr0: Reg<u32, _RLR0>

0x80 - HSEM Read lock register

rlr1: Reg<u32, _RLR1>

0x84 - HSEM Read lock register

rlr2: Reg<u32, _RLR2>

0x88 - HSEM Read lock register

rlr3: Reg<u32, _RLR3>

0x8c - HSEM Read lock register

rlr4: Reg<u32, _RLR4>

0x90 - HSEM Read lock register

rlr5: Reg<u32, _RLR5>

0x94 - HSEM Read lock register

rlr6: Reg<u32, _RLR6>

0x98 - HSEM Read lock register

rlr7: Reg<u32, _RLR7>

0x9c - HSEM Read lock register

rlr8: Reg<u32, _RLR8>

0xa0 - HSEM Read lock register

rlr9: Reg<u32, _RLR9>

0xa4 - HSEM Read lock register

rlr10: Reg<u32, _RLR10>

0xa8 - HSEM Read lock register

rlr11: Reg<u32, _RLR11>

0xac - HSEM Read lock register

rlr12: Reg<u32, _RLR12>

0xb0 - HSEM Read lock register

rlr13: Reg<u32, _RLR13>

0xb4 - HSEM Read lock register

rlr14: Reg<u32, _RLR14>

0xb8 - HSEM Read lock register

rlr15: Reg<u32, _RLR15>

0xbc - HSEM Read lock register

rlr16: Reg<u32, _RLR16>

0xc0 - HSEM Read lock register

rlr17: Reg<u32, _RLR17>

0xc4 - HSEM Read lock register

rlr18: Reg<u32, _RLR18>

0xc8 - HSEM Read lock register

rlr19: Reg<u32, _RLR19>

0xcc - HSEM Read lock register

rlr20: Reg<u32, _RLR20>

0xd0 - HSEM Read lock register

rlr21: Reg<u32, _RLR21>

0xd4 - HSEM Read lock register

rlr22: Reg<u32, _RLR22>

0xd8 - HSEM Read lock register

rlr23: Reg<u32, _RLR23>

0xdc - HSEM Read lock register

rlr24: Reg<u32, _RLR24>

0xe0 - HSEM Read lock register

rlr25: Reg<u32, _RLR25>

0xe4 - HSEM Read lock register

rlr26: Reg<u32, _RLR26>

0xe8 - HSEM Read lock register

rlr27: Reg<u32, _RLR27>

0xec - HSEM Read lock register

rlr28: Reg<u32, _RLR28>

0xf0 - HSEM Read lock register

rlr29: Reg<u32, _RLR29>

0xf4 - HSEM Read lock register

rlr30: Reg<u32, _RLR30>

0xf8 - HSEM Read lock register

rlr31: Reg<u32, _RLR31>

0xfc - HSEM Read lock register

ier: Reg<u32, _IER>

0x100 - HSEM Interrupt enable register

icr: Reg<u32, _ICR>

0x104 - HSEM Interrupt clear register

isr: Reg<u32, _ISR>

0x108 - HSEM Interrupt status register

misr: Reg<u32, _MISR>

0x10c - HSEM Masked interrupt status register

cr: Reg<u32, _CR>

0x140 - HSEM Clear register

keyr: Reg<u32, _KEYR>

0x144 - HSEM Interrupt clear register

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