Struct stm32h7xx_hal::stm32::ethernet_dma::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub dmamr: Reg<u32, _DMAMR>,
    pub dmasbmr: Reg<u32, _DMASBMR>,
    pub dmaisr: Reg<u32, _DMAISR>,
    pub dmadsr: Reg<u32, _DMADSR>,
    pub dmaccr: Reg<u32, _DMACCR>,
    pub dmactx_cr: Reg<u32, _DMACTXCR>,
    pub dmacrx_cr: Reg<u32, _DMACRXCR>,
    pub dmactx_dlar: Reg<u32, _DMACTXDLAR>,
    pub dmacrx_dlar: Reg<u32, _DMACRXDLAR>,
    pub dmactx_dtpr: Reg<u32, _DMACTXDTPR>,
    pub dmacrx_dtpr: Reg<u32, _DMACRXDTPR>,
    pub dmactx_rlr: Reg<u32, _DMACTXRLR>,
    pub dmacrx_rlr: Reg<u32, _DMACRXRLR>,
    pub dmacier: Reg<u32, _DMACIER>,
    pub dmacrx_iwtr: Reg<u32, _DMACRXIWTR>,
    pub dmaccatx_dr: Reg<u32, _DMACCATXDR>,
    pub dmaccarx_dr: Reg<u32, _DMACCARXDR>,
    pub dmaccatx_br: Reg<u32, _DMACCATXBR>,
    pub dmaccarx_br: Reg<u32, _DMACCARXBR>,
    pub dmacsr: Reg<u32, _DMACSR>,
    pub dmacmfcr: Reg<u32, _DMACMFCR>,
    // some fields omitted
}

Register block

Fields

dmamr: Reg<u32, _DMAMR>

0x00 - DMA mode register

dmasbmr: Reg<u32, _DMASBMR>

0x04 - System bus mode register

dmaisr: Reg<u32, _DMAISR>

0x08 - Interrupt status register

dmadsr: Reg<u32, _DMADSR>

0x0c - Debug status register

dmaccr: Reg<u32, _DMACCR>

0x100 - Channel control register

dmactx_cr: Reg<u32, _DMACTXCR>

0x104 - Channel transmit control register

dmacrx_cr: Reg<u32, _DMACRXCR>

0x108 - Channel receive control register

dmactx_dlar: Reg<u32, _DMACTXDLAR>

0x114 - Channel Tx descriptor list address register

dmacrx_dlar: Reg<u32, _DMACRXDLAR>

0x11c - Channel Rx descriptor list address register

dmactx_dtpr: Reg<u32, _DMACTXDTPR>

0x120 - Channel Tx descriptor tail pointer register

dmacrx_dtpr: Reg<u32, _DMACRXDTPR>

0x128 - Channel Rx descriptor tail pointer register

dmactx_rlr: Reg<u32, _DMACTXRLR>

0x12c - Channel Tx descriptor ring length register

dmacrx_rlr: Reg<u32, _DMACRXRLR>

0x130 - Channel Rx descriptor ring length register

dmacier: Reg<u32, _DMACIER>

0x134 - Channel interrupt enable register

dmacrx_iwtr: Reg<u32, _DMACRXIWTR>

0x138 - Channel Rx interrupt watchdog timer register

dmaccatx_dr: Reg<u32, _DMACCATXDR>

0x144 - Channel current application transmit descriptor register

dmaccarx_dr: Reg<u32, _DMACCARXDR>

0x14c - Channel current application receive descriptor register

dmaccatx_br: Reg<u32, _DMACCATXBR>

0x154 - Channel current application transmit buffer register

dmaccarx_br: Reg<u32, _DMACCARXBR>

0x15c - Channel current application receive buffer register

dmacsr: Reg<u32, _DMACSR>

0x160 - Channel status register

dmacmfcr: Reg<u32, _DMACMFCR>

0x16c - Channel missed frame count register

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