Struct stm32h7xx_hal::pac::rtc::RegisterBlock[][src]

#[repr(C)]pub struct RegisterBlock {
    pub tr: Reg<u32, _TR>,
    pub dr: Reg<u32, _DR>,
    pub cr: Reg<u32, _CR>,
    pub isr: Reg<u32, _ISR>,
    pub prer: Reg<u32, _PRER>,
    pub wutr: Reg<u32, _WUTR>,
    pub alrmar: Reg<u32, _ALRMAR>,
    pub alrmbr: Reg<u32, _ALRMBR>,
    pub wpr: Reg<u32, _WPR>,
    pub ssr: Reg<u32, _SSR>,
    pub shiftr: Reg<u32, _SHIFTR>,
    pub tstr: Reg<u32, _TSTR>,
    pub tsdr: Reg<u32, _TSDR>,
    pub tsssr: Reg<u32, _TSSSR>,
    pub calr: Reg<u32, _CALR>,
    pub tampcr: Reg<u32, _TAMPCR>,
    pub alrmassr: Reg<u32, _ALRMASSR>,
    pub alrmbssr: Reg<u32, _ALRMBSSR>,
    pub or: Reg<u32, _OR>,
    pub bkpr: [Reg<u32, _BKPR>; 32],
    // some fields omitted
}

Register block

Fields

tr: Reg<u32, _TR>

0x00 - The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.

dr: Reg<u32, _DR>

0x04 - The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.

cr: Reg<u32, _CR>

0x08 - RTC control register

isr: Reg<u32, _ISR>

0x0c - This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9.

prer: Reg<u32, _PRER>

0x10 - This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9.

wutr: Reg<u32, _WUTR>

0x14 - This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9.

alrmar: Reg<u32, _ALRMAR>

0x1c - This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.

alrmbr: Reg<u32, _ALRMBR>

0x20 - This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.

wpr: Reg<u32, _WPR>

0x24 - RTC write protection register

ssr: Reg<u32, _SSR>

0x28 - RTC sub second register

shiftr: Reg<u32, _SHIFTR>

0x2c - This register is write protected. The write access procedure is described in RTC register write protection on page9.

tstr: Reg<u32, _TSTR>

0x30 - The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.

tsdr: Reg<u32, _TSDR>

0x34 - The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.

tsssr: Reg<u32, _TSSSR>

0x38 - The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset.

calr: Reg<u32, _CALR>

0x3c - This register is write protected. The write access procedure is described in RTC register write protection on page9.

tampcr: Reg<u32, _TAMPCR>

0x40 - RTC tamper and alternate function configuration register

alrmassr: Reg<u32, _ALRMASSR>

0x44 - This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9

alrmbssr: Reg<u32, _ALRMBSSR>

0x48 - This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection.

or: Reg<u32, _OR>

0x4c - RTC option register

bkpr: [Reg<u32, _BKPR>; 32]

0x50 - RTC backup registers

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